Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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PCB design constrain issue

Altera_Forum
Honored Contributor II
‎06-15-2011 03:35 AM
1,000 Views

Hi Dears: 

 

I found that the GXB pairs' space of ALTERA'a StratixIIGX's SI devkit were constrained to 35 mils, which confused me. 

 

In normal, in my opinoin, this is constrain to about 10 mils. Why altera gave such large constrain.
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