PCI Express HARD IP implementation using STRATIX IV FPGA

[Altera_Forum]

Hi, 

I am working on an academic project in which i am using PCI Express HARD IP of stratix IV device (EP4SGX70DF29C3N). To implement this, i am using MegaWizard Plug-In Manager. I am using quartus II 11.0 sp1 (32-bit) software. I have generated the .vhd file and trying to simulate it on Altera's ModelSim 6.6d but unable to simulate. so anyone please help me ASAP.  Thank you,  with regards, amit

[Altera_Forum]

For simulation please press "SIMULATE" button.

[Altera_Forum]

hii, 

sorry to say but i didn't mean that i don't know to PRESS the SIMULATE BUTTON in modelsim. my problem is that i don't know the exact input values and their correct sequence to simulate it. i have already gone through the document "IP Compiler for PCI Express user guide" of altera. also i have reffered the "PCI Express High Performance Reference design" document of altera but in this they have used QSYS approach. but i want megawizard plug-in manager approach. so please give me a solution. Design

[Altera_Forum]

hi, can anybody help me with the test bench for pci express hard ip implementation using stratix iv fpga in megawizard plug-in manager.

[Altera_Forum]

IIRC the PCIE BFM is not available in Quartus 11.0. You will need to upgrade to 12+ to get the BFM for simulation.

[Altera_Forum]

hii,  

sorry for my late reply. and thanks for your reply. now i am trying to update quartus to 12+ version.  thank you.

[Altera_Forum]

hii, 

i would like to know that is it possible to disable some of the pins(input/output) of pcie hard ip of stratix iv of quartus ii software. please help asap.

[Altera_Forum]

hii, 

please anyone help me for the above mentioned problem(s).

[Altera_Forum]

What kind of pins are you trying to disable. 

 I presume you are building an endpoint, not a switch or hub, so yes, you can disable some of the lanes, you do not have to use it with all 8. Besides that, depending on how you build it in the Wizard, a few pins are optional. For error checking for example you can use the tx_err or the fancier ECRC. there is also The mask bits you can use but are not obliged to. For the interrupt mechanism you can use any of legacy, legacy + MSI, or legacy + MSI + MSI-X. Besides that I think you have to use it all.  Do you mean you are having too many pins to implement it in the FPGA? In that case perhaps your synthesis is not set-up right. When you build the Hard-IP you get the simulation version that has several pins that do not exist in the IP, like the pipemode version of the lanes. If you try to synthesize that you will get a huge number of extra pins. You have to synthesize the version intended for synthesis.  -G

[Altera_Forum]

hii, actually i am buildind a root port not an end point. its a pcie x1 gen2 design.

[Altera_Forum]

HII, 

Is there any reference design of IP Compiler for PCIe HARD IP Implementation using MegaWizard Plug-In Manager?? Because on altera's site they have given the high performance reference design using Qsys. please reply ASAP. thank you.

[Altera_Forum]

hii, 

please anyone help me for the above query.

[Altera_Forum]

And why don't You want to use Qsys? Take that design as reference.

[Altera_Forum]

hii, 

actually in qsys, i am unable to find 64-bit parallel i/o.. this might be silly question for you but i am unable to find. but in megawizard plug-in manager, its available. so please guide me.

[Altera_Forum]

--- Quote Start ---  hii, actually i am buildind a root port not an end point. its a pcie x1 gen2 design.  --- Quote End ---    IT does not matter if it is a root port or an endpoint. In the end the problem is the same. You have to make sure you use the correct file for simulation and the correct file for synthesis. The main .v (or vhd) that shows up in the directory has a few hundred ports that apply only in simulation. In the examples <...>_examples/chaining_dma/...._top.v file you see the top level file instantiated in side another block and that one is the top that the example uses. You will see all the simulation only pins floating.  My question to you is if you made sure those simulation only ports (txdatak, txelecidle, etc) are not being ported out. If they are you need to remove them from the ports. The actual IP will have only the lanes (rx_in/tx_out) a few reference clocks and some overhead signals that need to go to the pins. The other side, that talks to your application layer, of course will need to be connected internally to whatever you designed.