Hi,
We are doing PCI Express to local Bus conversion in Stratix 4 FPGA. Our board has a processor(master) which gives out PCIe Link to the FPGA. Inside FPGA we are converting this PCIe link into local bus. The above processor can access memories and peripherals through this local bus. We have connected PCI Express Hard IP to the tri-state bridge through SOPC builder. We have connected the PCIe BAR- Avalon MM master to the Avalon slave in tri-state bridge. We are facing the following problems:
1. PCI Express Compiler is having TX_interface- Avalon MM slave. What it means? What should we do with this?
2. PCI Express Compiler is having control_register_access- Avalon MM slave. What it means? What should we do with this?
3. Otherwise please tell us about the PCI express to local bus conversion inside Stratix 4 FPGA.
4. Is there any soft IP available for PCIe to Local Bus Conversion? IF any pls tell us about the same.
