PCIe hard ip write BAR0 without control.

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PCIe hard ip write BAR0 without control.

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Who know the reason?

When i test the PCIe example(create by pcie hard ip), you can find it in <your project dir>\PCI_examples\chaining_dma.

You program it in FPGA, Then test it with WINDRIVER.

first you wirte 0x11111111 to offset 0 in BAR0(for example), then you read the same address. you can get 0x11111111.

But, after some minutes, what you read is 0x00000083 or 63.

who know the reason?

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