PDN Tool - What is core clock frequency

[AnuragSH]

I am using Stratix 10 device and wanted to know what exactly  the "Core Clock Frequncy" refers to in the PDN 2.0.?

Is it the Core power supply regulator switching frequency or the FPGA Core reference frequency or something else?

PDN guide shows what to select (like low, medium, high, custom) but doesn't explain what it is. I have not been able to find any document in the website related to this topic.

Please let me know what it is or point to the document where it is explained.

[Ash_R_Intel]

Hi,

Core Clock Frequency refers to an average frequency on which your FPGA logic will work. This is the part of design other than blocks like transceivers, hard memory blocks, HPS, etc..

Regards

[AnuragSH]

Thank you,

One additional question related to PDN:

In PDN the "Current Ramp Up Period" is mention interms of cycles, what does each cycle represent?

[Ash_R_Intel]

Hi,

The Current Ramp Up Period parameter allows you to specify the number of clock

cycles consumed by the pipeline. You can select a Long, Medium, Short, or Custom

setting.

The pipeline registers in the design impact the power drawn. Refer section 1.2.2.1.6 of the user guide for its description: https://www.intel.com/content/www/us/en/docs/programmable/683293/current/rail-group-summary-section.html

Regards