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PFL core and PS configuration mode


I have chosen my Flash memory (MX25L12833F: QUAD SPI Flash from Macronix) and the CPLD will be MAX10. this flash is not listed in supported flashes in the document UG-01082 2018.08.06 (since most of those are listed as not recommended for new design in the manufacturer website!) but newer version of one listed in table 2.

I have two questions or uncertainties, hopefully you can help me on those as well.

  1. Do you think this flash will work with PFL core without any problem? I have checked the manufacturer website for the differences and looks to me, it should not make any problem.
  2. based on the parameters that the core needs to be completed, it looks the PFL core can generate the right communication through SPI interface with the flash so I shouldn't be worried about the command format in both modes: read and write. Is that correct?
  3. I am confused about paging and having different configuration files in separate pages in flash. I can see some flashes supports page read/write. is this what PFL core needs to have different files in the flash or just as long as the size is enough for all configuration files, the core will handle the reading the right configuration file through the parameter fpga_pgm[]? the reason I am asking, I see for only some of the listed memories in the document, has been listed supports paging.

Thanks for your help


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3 Replies

Hi HT,


Intel recommendation :When connecting quad SPI flashes in parallel, use identical flash memory devices with the same memory density from the same device family and manufacturer.


  1. MX25L12833E is Intel recommended flash and supports PFL but MX25L12833E is discontinued by Macronix and recommends MX25L12835F. We are not seeing major difference between MX25L12833F & MX25L12835F other-than Software Features & Technology.So PFL may work fine with flash.
  2. Yes, PFL will communication through SPI interface with the flash.the PFL logic in Intel CPLDs as a configuration controller for FPGA configuration. The PFL logic in the CPLD determines when to start the configuration process, read the data from the flash memory device, and configure the Intel FPGA in PS or FPP configuration scheme.
  3. The pages allow you to store designs for different FPGA chains or different designs for the same FPGA chain in different pages, The total number of pages and the size of each page depends on the density of the flash.Refer ug_pfl.pfd for mmore information


Let me know if you need any further assistance.


Best Regards,



Thanks for your explanation.

Still the paging is confusing for me. in Altera document, the flashes from Macronix (table 1 and 2) have not been listed with page mode capability but I can see they have the feature page read/write. do you think it is ok? can I save multiple configuration file in the chosen flash?

Many thanks,



Hi Hamid,


The MX25L12833F & MX25L12835F flashes from Macronix are not tested by intel. We can not guarantee on performance.

But however i think read/write should work & you can program multiple configuration file.