PHY Control - access

[Altera_Forum]

Hello!! I'm very new in this fpga word and I'm trying to learn more about this world. I'm with a project that I'm getting 16 bit data already packet and ready to send, I don't have to implement the mac address and all this stuff, I only have to send the data... My problem is the documentation about marvell 88e1111 is pretty pour and for me is being imposible to carry on with this developement.  

 I create one state machine that sends 16 bit in 4 diferent packets to the PHY conector, and I alse put the gtx clk, the mdio, mdc to ground and after that I tried to snif the data with wireshak. I'm getting nothing there and I don't know why, the state machine is working in my signaltap, and is sending and first 4 bits, then zeros, the 4 bits... but it doesn't mean that my transmision is working because is not, I don't know if the problem is that I have to do something with mdio or not :S    If you have any tip it will be great!!! please don`t tell "use an ip core" because I cant, I don't want MAC access!!  Thans for all :)

[Altera_Forum]

Well if you are reading back your packets with Wireshark, you will need a compliant Ethernet packet with a complete header, including the preamble, source and destination MAC addresses and Ethertype, and the CRC at the end. Without that the Ethernet packet will be dropped by the PC's network card and you won't see it in Wireshark. 

If you are using one of Altera's development kit, the PHY chip is wired to start automatically the autonegotiate process after reset, so you shouldn't need to do anything on MDIO. Just ensure that you know what speed was negotiated and that you are using the proper clock frequency and interface protocol in accordance with the link speed.