PI controller in VHDL

[Altera_Forum]

I'm trying to implement a PI controller in VHDL. where i tried a lot but i failed 

Please, can any one help me to achieve this task where i'm new in this field.

[Altera_Forum]

what code are you struggling with?

[Altera_Forum]

I have done sort of PI that consisted of two branches only (proportional and integral parts). I used it for phase error control in a receiver carrier tracking. 

 It was very simple in vhdl (but have the code misplaced). The proportional part is just a multiplier; you multiply the error(input) by a constant (I used .1 ~ 200). The integral part is just an acuumulator; you add up the error nonstop and hopefully will not overflow. You will need to add a term here to decide how much to feedback = leakage (e.g. .001 ~ 1), again needs multiplier in the accumulator loop. The two branches are just added up.  Testing is more difficult and best is in-system testing

[Altera_Forum]

Thanks very much for your replies. 

 thanks Kaz i understand the proportional term but rely i didn't understand the integral term. can you explain it again and with its equation?  note: for the proportional term there no value for sampling time.

[Altera_Forum]

i would like to tell you the equation of PI controller that i used: 

 u(k)=u(k-1) + err(k)*(kp +(ki*ts/2)) + err(k-1) * ( (ki*ts/2) - kp)  where:   u : is the output of controller.  err: error signal that injected to the controller.  kp: proportional constant.  ki : integral constant.  ts : sampling time.

[Altera_Forum]

I believe your equation is different from what described previously about my experience. 

 I had a go at it and hope it is correct. see attached diagram.

[Altera_Forum]

The PI controller algorithm presented by maha.eg can be found quite often in literature, it's also quoted as velocity algorithm, because the controller output u(k)-u(k1) represents the change rate of manipulated value. It's main advantage is that it allows to stop integration exactly at the limits of the manipulated value u(k). 

 Besides the shown variant of the algorithms, which refers to trapezoidal integration, there's also a rectangular integral variant. My digital control text book mentions, that the difference between both is neglectable for short sample periods.   u(k)=u(k-1) + err(k)*kp + err(k-1) * (ki*ts - kp)

[Altera_Forum]

Thanks Kaz and FvM for your replies 

 Kaz your diagram describe my equation, does this mean that my equation is correct and can be used? but i can't get the experimental results where i'm programming the equation in FPGA by VHDL language.   FVM thanks for your reply, but do you mean from your equation that i must replace my equation by your equation. please clear for me what is your idea?  thanks very much for all.

[Altera_Forum]

I don't know about the equation, I just copied it from you. 

Whether it correct or know, I think FvM confirmed it and he is really the Guy who knows about all that techno stuff.  But I implemented it as diagram. You need to make sure you get your computation are correct especially issues of truncating bits at results.  You need a math model and simulate first before you move to actual real time system

[Altera_Forum]

I have attached a paper that I wrote some time ago with significant details for PI controller implementation in VHDL, but also considers bit growth, testing philosophy, dynamic range, etc. This paper has been widely read. 

 James

[Altera_Forum]

Thanks james for you reply. I will study this paper.

[Altera_Forum]

One of the key issues in implementing this type of controller is how to handle the clamping function. Think about how to wrap a finite state machine controller around the main PI; to enable the integrator after the clamp has cleared in an appropriate manner. This topic is in addition to how to handle the bit growth of the accumulator; which is an issue in any FIR or IIR filter design. -James

[Altera_Forum]

Hi, 

what about the relationship between Kp, Ki, Kd and the width of the input signals? For example if i have input data coming from a 12bit ADC with 5V analog range and a 12bit ADC with 2.5V analog range (so the same input voltage is rapresented with different words) are the PI parameters affected by this?

[Altera_Forum]

The ADC and DAC scaling isn't part of the digital controller, but it obviously affects the feedback loop gain. I think the plant model should take account of it.

[Altera_Forum]

Hello James, 

 I have to design a pid servo for power stabilization of the lasers . I have thought of the closed loop design involving the experiment and the feedback. I read your paper on the pid controller and was wondering about what should be the sampling interval for the integral component and how to implement it in vhdl. My ADC's and DAC's work at maximum frequency of 10 MHz and 25 MHz respectively. Does that mean for the PID , I can have a maximum frequency of 12.5 MHz (half the frequency of DAC). Secondly, how to use the inverse of this frequency (sampling interval) in the difference equation that you have given in your paper. Thanks.