Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21594 Discussions

PIPE IF provided in ARRIA GX FPGA

Altera_Forum
Honored Contributor II
‎11-26-2008 07:00 AM
983 Views

Does the Rate Matcher provided in PIPE IF in Arria GX device add / remove SKP characters in received SKIP Ordered sets simultaneously on all lanes is configured as a x4 link?  

 

or each lane preforms this clock compensation individually.... 

 

Regards, 

 

Pavan
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.