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PIPE IF provided in ARRIA GX FPGA

Altera_Forum
Honored Contributor II
‎11-26-2008 07:00 AM
1,011 Views

Does the Rate Matcher provided in PIPE IF in Arria GX device add / remove SKP characters in received SKIP Ordered sets simultaneously on all lanes is configured as a x4 link?  

 

or each lane preforms this clock compensation individually.... 

 

Regards, 

 

Pavan
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