PLL_CLKOUT Jitter

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PLL_CLKOUT Jitter

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I understand that to minimize jitter when driving an output pin with a PLL that the dedicated PLL_CLKOUT pin should be used, and that it's advisable to ground nearby pins to reduce crosstalk. On an EP3C5 device in a U256 package, what are the preferred pins to ground?

A related question; I'd really like to have two different outputs of the same PLL drive output pins. In this case what is the best choice for the second output? Which are the best nearby pins to ground?

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