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PLL Implemantation

Altera_Forum
Honored Contributor II
1,866 Views

Hi, 

 

During the compilation of a quartus design, the following messages appears: 

 

Warning: PLL "pll_name" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input 

 

Warning: PLL "pll_name" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins 

 

Warning: PLL "pll_name" output port clk[0] feeds output pin "pin_clk_dac_1" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance 

 

I need the best jitter performance, but I don't know how to "dedicate" the input and output pin of the PLL... 

(The input is a an input of the design, the output as well, there is no signal between) 

 

Thanks!
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7 Replies
Altera_Forum
Honored Contributor II
222 Views

You can't "dedicate" the input and output pins of a PLL they are hard wired to pins and defined in the pin out files for each FPGA.

Altera_Forum
Honored Contributor II
222 Views

I think we're mixing up names(which is understandable since Altera mixes them up since switching to TimeQuest and using their nomenclature.) The pin in the message is a top-level IO connection on your board. In TimeQuest, this is called a port, and the pin is the input/output connections of the actual PLL in the silicon. As Ben mentioned, the PLL pins in the silicon are dedicated. 

But getting to those PLL pins from the user I/O(i.e. ports) can be done directly or circuitously. There are dedicated clock pins that drive the PLL directly, and each PLL has dedicated output pins to drive clocks off chip. (I'm not sure what device, but look at the handbook for more details). These are the ports you want to use. If you assign your I/O to anything else, then Quartus has to find a way from these I/O to/from the PLL, i.e. it uses generic routing resources that will add jitter. (I don't think the jitter will be huge though, just that it could be better. My biggest concern is the route to the PLL, since this route will not be compensated for by the PLL.) 

So if your board isn't laid out, then please make these modifications. (You could use the pin-planner, but to be honest, just unassign these pins and I believe Quartus will choose the more direct path by default, assuming nothing else is using them). If you really need the best jitter, I believe the no-compensation setting of the PLL is best. The handbook should discuss this. I've never seen anyone use this because the jitter has always been really good with other compensation modes, but just pointing it out.
Altera_Forum
Honored Contributor II
222 Views

Follow Rysc's suggestions about using the device pins that are dedicated for the PLL input and output functions. If you are getting the warnings with the dedicated pins, check whether you have a Global Signal setting on the clock signals in question. 

 

I had a case where the PLL used a dedicated clock input pin that the Stratix II handbook said was associated with that PLL. Even with the correct combination of pin and PLL, a Global Signal setting caused the jitter warning. Forcing global usage with that setting resulted in an indirect route from the dedicated clock input pin to the global buffer to the PLL. Altera said that the PLL can't compensate for the additional delay caused by the global clock routing between the device pin and the PLL (note that this is not a problem for the internal destinations of a PLL being on global routing). With the Global Signal setting removed or set to off, the Fitter was allowed to use the dedicated routing from the dedicated pin to the PLL. If you have no Global Signal setting at all, the Fitter will probably use the global routing where it needs it and not use it for the pin-to-PLL connection. If you need the Global Signal setting on to force global usage for some things driven by the dedicated clock input pin, you can use a point-to-point setting to turn it off for just the path from the pin to the PLL. 

 

I suspect the same situation can occur for a PLL output. 

 

 

I asked Altera to add a statement about this cause of the warning to the help page for the message. Here's how the help looks in QII 7.2: 

 

 

--- Quote Start ---  

PLL "<name>" input clock inclk[<number>] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input 

 

-------------------------------------------------------------------------------- 

 

CAUSE: The specified PLL's input clock is not driven by a dedicated input pin. As a result, the input clock delay will not be fully compensated by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. this can also occur if a global signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.  

 

ACTION: If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or assign the input pin only to a dedicated input clock location for the PLL. If you do not want compensation of the specified input clock, then set the PLL to No Compensation mode.  

 

--- Quote End ---  

Altera_Forum
Honored Contributor II
222 Views

Hi, 

 

I am testing out a design on the stratix II gx PCIe dev. board and found out the same warning during the fitter process 

 

warning: pll "pll_25m:pll_25m|altpll:altpll_component|pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input 

 

Based on the stratix II gx part no EP2SGX901508C3 pin information, bank 13 and 14 have no PLL. However, I see two differential clocks, 156.25 and 155.52 in to banks 14 (pin H7,H8) and 13 (pin P7,P8) respectively. I am using these clocks to generate 100 and 125 MHz respectively with PLL(s) and the synthesis complains about the inputs with the warning above for both PLL(s). 

 

Apparently the board design did not use dedicated PLL inputs for the above clock inputs.  

 

Please advise how to turn it off. 

 

Thanks, 

Fasahat
Altera_Forum
Honored Contributor II
222 Views

Ignore the warning.

Altera_Forum
Honored Contributor II
222 Views

 

--- Quote Start ---  

Ignore the warning. 

--- Quote End ---  

 

 

What if it's a critical warning? :o  

 

I have this design on Cyclone 3 that has a clock (14MHz) input from a dedicated clock pin, prompted as global clock by the fitter automatically because it is used in many places. Then this clock is used as the input for two plls to generate 3 other clocks (can't be merged into 1 pll). Now the fitter is giving the same warning was discussed in this thread but it's critical. Can it be ignored? What does the compensation do anyway? 

 

I also tried cascade the plls in a way that the clock pin is connected to one of the plls, and that pll generates another 14MHz clock which is used as an input for the second pll and also for being used in the other part of the design. That doesn't seem to work well because it takes much longer to fit and when it does finish fitting I got many timing violations.... Don't know if it's related to the clock tree change. Any thoughts? 

 

Hua
Moki
Beginner
222 Views

I had a similar problem, because my input clock was marked as a global clock.

 

Removing this from my .qsf file solved the issue:

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk

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