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PLL Phase Shifting design

Altera_Forum
Honored Contributor II
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The purpose of this design is to allow the phase bumping of a PLL as specified in AN367: Implementing PLL Reconfiguration in Stratix II Devices http://www.altera.com/literature/an/an367.pdf. The major differences being: 

- This design only allows for phase bumping of the PLL as described on pages 8-11 of AN367 

- This design does not require the use of the altpll_reconfig megafunction as described in AN367, just a simple register interface 

- This design only uses logic for storage of the PLL configuration bits (< 20 registers and 40 ALUTs); no RAMs or ROMs are used
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Altera_Forum
Honored Contributor II
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Can you add the design files (.qar, .v) and the .pl script?

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SLabe
Partner
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Hello, where can we find the files referenced in the posted Word Document? Thank you!

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