I'm trying to cascade 2 plls on the Cyclone V (5CEBA2F23C8). Both integer. I set the first to have a cascade_out and the 2nd to have adjpllin. Then I connect these.Even with an otherwise empty project the fitter claims this does not fit in the device. The only other reference to adjpllin I can see on this forum is complaining of the same problem! http://www.alteraforum.com/forum/showthread.php?t=44368&highlight=adjpllin. I had built it like the schematic in this thread. So is pll cascading broken in Cyclone V or is there a workaround? I've checked the device manual and it seems I am doing everything right - but it does not work. I tried upgrading quartus and the ip from 15.0 to 16.1 with no improvement. The actual errors I receive are as follows: Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (1 PLL output counter(s), 1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 fractional PLL, which is within Altera PLL pll_amult. Info (14596): Information about the failing component(s): Info (175028): The fractional PLL name(s): pll_amult:pll_amult_inst|pll_amult_0002:pll_amult_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll Error (16234): No legal location could be found out of 4 considered location(s). Reasons why each location could not be used are summarized below: Error (177014): Invalid port found on the path from source PLL output counter output to the fractional PLL Info (175026): Source: PLL output counter pll_acore:pll_acore_inst|pll_acore_0002:pll_acore_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter.output_counter Error (11179): The PLL output counter could not be placed in any location to satisfy its connectivity requirements Error (11179): The fractional PLL could not be placed in any location to satisfy its connectivity requirements Info (175029): 4 locations affected Info (175029): FRACTIONALPLL_X0_Y1_N0 Info (175029): FRACTIONALPLL_X0_Y38_N0 Info (175029): FRACTIONALPLL_X54_Y1_N0 Info (175029): FRACTIONALPLL_X54_Y38_N0 Error (175001): The Fitter cannot place 1 PLL output counter, which is within Altera PLL pll_acore. Info (14596): Information about the failing component(s): Info (175028): The PLL output counter name(s): pll_acorell_acore_inst|pll_acore_0002ll_acore_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter.output_counter Error (16234): No legal location could be found out of 36 considered location(s). Reasons why each location could not be used are summarized below: Error (175005): Could not find a location with: FPLL_OUTPUT_COUNTER_ADJPLLIN_CONNECTION (36 locations affected) Info (175029): PLLOUTPUTCOUNTER_X0_Y0_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y1_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y2_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y3_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y4_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y5_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y6_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y7_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y8_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y37_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y38_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y39_N1 Info (175029): and 24 more locations not displayed Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
I tried with some larger devices and found that it does not synthesize on the Cyclone V E A2 and A4 - but it does on the A5,A7,A9.On the device datasheet the number of plls increase after the A4 (A2:4,A4:4,A5:6,A7:7,A9:8). So I guess pll cascading is not supported on the 4 pll Cyclone V E devices. Is this down to the lack of a 'pll strip'? I wonder if this is a Quartus bug or just the devices do not support this. I can't find anything in the device manual or family overview.
A quick note that I found this is simply not needed on cyclone V, since its possible to connect the output of one pll to the input of another anyway. Which just simply works.