PLL clock output pins vs. regular I/O pins?

[Altera_Forum]

This is a question about whether to use the actual PLL clock output pins of the FPGA, or to simply continue using regular I/O pins to output clock signals, and the pros/cons of each option. 

 Specifics Using a Cyclone IV E device and I have 2 interfaces that require outputing a clock off chip. 1. An LVDS bus using ALTLVDS_TX, with 4 data lines at 7:1 serialization and 1 clock line . This is actually a "camera link" video interface. 2. A source synchronous parrallel bus output to another chip, with a clock that should be 180 degrees shifted from the data transitions.  In the first version of my board I just used regular I/O pins for both clock signals. In case 2, I generate a 180 shifted copy of the clock from the PLL and send that to the regular output pin. For case 1, the clock comes from the ALTLVDS_TX macro.  The big question is: for the next board, should I be using the PLL clock output pins for these? What are the pros/cons? Since the output pins are actually labeled, "PLL1_ouptput , PLL2_output"... I would need to know exactly which PLL will be used. How would I know that?   Thanks! J

[Altera_Forum]

The advantage of the PLL output pins is that they have dedicated, characterised routing. This allows you to, very accurately, control the phase of the clocks being driven from these pins. This becomes a major advantage particularly if you're clocking a synchronous interface to another device. This sounds relevant for both your interfaces. 

 As soon as you drive a PLL clock out of a standard I/O pin you're subject to all the routing delays incurred in getting the clock to the I/O pin. Depending on your clock frequency, you're likely to find it very difficult to constrain your design appropriately.  Have a read of the 'cyclone iv pll hardware overview' section, page 5-20, in the clock networks and plls in cyclone iv devices (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51005.pdf) chapter of the Cyclone IV datasheet.  As for which PLL will be used (from the same datasheet):   --- Quote Start ---  Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.  --- Quote End ---  and 'PLL1_output' is associated with PLL1 etc.  Cheers, Alex