PLL clock output

[Altera_Forum]

Hi, 

 My design needs the PLL-clock output to be mapped to non-dedicated clock output pin of FPGA. When I do so, the following error message appears. What would be the best solution?   Warning: PLL "pll_312M:u_pll_312M|altpll:altpll_component|pll_312M_altpll:auto_generated|pll1" output port clk[1] feeds output pin "PLL_OUTCLKP~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

[Altera_Forum]

It's not an error - it's a warning which you are guaranteed to get when driving non-dedicated pin with PLL output. If this is what you intended to do, you can simply ignore this warning.

[Altera_Forum]

Yeah, It was warning message only. Is there any option like inserting clock buffers as in Xilinx ??!!!

[Altera_Forum]

There's a clock control megafunction ALTCLKCTRL: http://www.altera.com/literature/ug/ug_altclock.pdf. 

PLL's outputs are already connected to global clock networks, so you don't need to implement any additional buffers.