PLL generation problem

[Altera_Forum]

Hi! 

I have a problem in realizing a PLL. I need a PLL that (with a 50 MHz in input) gives me 3 different clocks: CKSYS,CKPBWR,PCLK.  The first have no shift from the clock source.  CKPBWR must be NOT(CKSYS). The last one have a frequency of an half of clock source (25 Mhz).  All this three clocks are used internally, they don't drive any output pin of the FPGA(DE1 Board). I have tried to realize it with MegaWizard pug-in manager but I have more than one timings problem. This is the quartus warning: PLL cross checking found inconsistent PLL clock settings:  Warning: Clock: SYSCKSGen:SYSCKSGEN0|PLLSYS:PLLSYS0|altpll:altpll_component|_clk1 was found on node: SYSCKSGEN0|PLLSYS0|altpll_component|pll|clk[1] with settings that do not match the following PLL specifications:  Warning: -phase (expected: 180.00, found: 414.00)  Warning: Clock: SYSCKSGen:SYSCKSGEN0|PLLSYS:PLLSYS0|altpll:altpll_component|_clk2 was found on node: SYSCKSGEN0|PLLSYS0|altpll_component|pll|clk[2] with settings that do not match the following PLL specifications: Warning: -phase (expected: 0.00, found: 27.00)    I have attached the PLL source code generated by altera plug-in any suggestions?

[Altera_Forum]

Hi, 

those are TimeQuest messages, IIRC. The constraints in the .SDC file don't match the settings in your PLL compoment.  You need to 1. constrain the input clock with "create_clock". 2. use "derive_pll_clocks" to constrain the PLL outputs

[Altera_Forum]

I have the same problem (same warnings), but what I found is: 

 After a compilation with Design Space Explorer I modified the phase of two generated clocks in two PLLs. Then I ran Analysis&Synthesis and the Fitter, started TimeQuest and generated a new .sdc-File with my own .sdc-File-Template. My Template defines all clocks in the design and derives the generated clocks (well it did before the compilation with DSE). But now the TimeQuest Analyzer generates me a .sdc-File with the old Values of the PLLs. And when I modify the generated clocks to match the implemented PLLs, Quartus only tells me that Warning. (With expected: <old value>, found: <new value>)  Any Idea?