PLL output delay

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PLL output delay

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Hi :

I am using the PLL of Cyclone. The mode I choose is no compensation.

I have a question:

What is the delay from the external input clock pin to the internal output port? The output port is connected to the internal clock network and will be divided. Finally, the devided signal is output from the IO port.

So the delay is need to be known or estimated beforehand.

Thanks in advance!

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