PLL question about Cyclone III EP3C16

[Altera_Forum]

Hi, all, 

 Currently I am designing a board with Cyclone III FPGA EP3C16. And I want to use the PLL function. When I check the Pin function, there are always two pins for PLL Clock out. One is PLL_CLKOUTp, the other is PLL_CLKOUTn. I believe it is designed for differential CLK. But I just use the single CLK. Is that I should use PLL_CLKOUTp? By the way, whether I can use PLL_CLKOUTn as standard I/O?   Thanks,

[Altera_Forum]

http://www.altera.com/literature/dp/cyclone3/ep3c16.pdf 

 Looks like you can use PLL_CLKOUTp as a single-ended output. Not sure if you can use PLL_CLKOUTn as a user I/O if using PLL_CLKOUTp as a PLL clock output. A simple test build would answer that question.   Another handy document is: http://www.altera.com/literature/dp/cyclone3/pcg-01003.pdf

[Altera_Forum]

Thanks, gmpstr!