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Altera_Forum
Honored Contributor I
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PLL reconfig on Cyclone V stops responding

I am currently using a PLL on a Cyclone V device to generate a clock that is used to run a reasonably low frequency RF transceiver (class D amplifier and direct ADC sampling). As a part of general operation, the PLL is required to scan through a number of frequencies running some tuning tests at each one. 

 

I'm using the Altera PLL Reconfig IP core to reconfigure the PLL for each frequency. For the most part, it seems to be working OK, but every now and then it stops responding. I update the N/M/C counter registers and then write a 1 to the start register, but when I read back the counter registers they haven't changed. No matter what I try and set the counters to from that point forward, they do not change. 

 

I can recover from this scenario by reading a from the status register (which is weird given the reconfig core is in waitrequest mode). I attempted to hack around the issue by simply reading from the status register after each reconfiguration, but at some point this just caused the entire SoC to hang. 

 

The PLL is fed by a 20MHz TXCO (we've tested a 100MHz silicon oscillator, too), and the PLL is scanned across a range of 64MHz to 128MHz. 

 

I wrote a simple Python script that picks a random frequency (and associated counter values) from a predefined set and attempts to set the PLL. If it fails, it dumps the current counter, reads and dumps the status register and then continues. It hasn't shed any light on what might be causing the issue, but here is what it outputs for posterity: 

Status = 0 Failed to change from 66666666 to 63846153 Hz after 8214 changes. Counters: (3, 100, 10) Status = 0 Failed to change from 64000000 to 63571428 Hz after 93 changes. Counters: (1, 32, 10) Status = 0 Failed to change from 76000000 to 64428571 Hz after 1394 changes. Counters: (1, 38, 10) Status = 0 Failed to change from 126000000 to 105200000 Hz after 571 changes. Counters: (1, 63, 10) Status = 0 Failed to change from 102000000 to 61375000 Hz after 4771 changes. Counters: (1, 51, 10) Status = 0 Failed to change from 113000000 to 66500000 Hz after 480 changes. Counters: (2, 113, 10) Status = 0 Failed to change from 63333333 to 75666666 Hz after 151 changes. Counters: (3, 95, 10) Status = 0 Failed to change from 96000000 to 70666666 Hz after 1212 changes. Counters: (1, 48, 10) Status = 0 Failed to change from 124666666 to 71800000 Hz after 178 changes. Counters: (3, 187, 10) Status = 0 Failed to change from 110000000 to 61866666 Hz after 2256 changes. Counters: (1, 55, 10) Status = 0 Failed to change from 74000000 to 108888888 Hz after 271 changes. Counters: (1, 37, 10) Status = 0 Failed to change from 112000000 to 114500000 Hz after 1725 changes. Counters: (1, 56, 10) Status = 0 Failed to change from 69333333 to 67066666 Hz after 1354 changes. Counters: (3, 104, 10) Status = 0 Failed to change from 122000000 to 118750000 Hz after 572 changes. Counters: (1, 61, 10) Status = 0 Failed to change from 69000000 to 82500000 Hz after 3336 changes. Counters: (2, 69, 10) Status = 0 Failed to change from 75000000 to 120400000 Hz after 14 changes. Counters: (2, 75, 10) Status = 0 Failed to change from 118000000 to 84571428 Hz after 1934 changes. Counters: (1, 59, 10) Status = 0 Failed to change from 86000000 to 65454545 Hz after 1641 changes. Counters: (1, 43, 10) Status = 0 Failed to change from 104000000 to 61666666 Hz after 3339 changes. Counters: (1, 52, 10) Status = 0 Failed to change from 102000000 to 64307692 Hz after 1022 changes. Counters: (1, 51, 10) Status = 0 Failed to change from 87000000 to 89333333 Hz after 376 changes. Counters: (2, 87, 10) Status = 0 Failed to change from 100000000 to 60769230 Hz after 4966 changes. Counters: (1, 50, 10) Status = 0 Failed to change from 128000000 to 98666666 Hz after 8567 changes. Counters: (1, 64, 10) Status = 0 Failed to change from 92000000 to 88666666 Hz after 942 changes. Counters: (1, 46, 10) Status = 0 Failed to change from 118000000 to 65636363 Hz after 124 changes. Counters: (1, 59, 10) Status = 0 Failed to change from 104000000 to 80444444 Hz after 4248 changes. Counters: (1, 52, 10) Status = 0 Failed to change from 73000000 to 67600000 Hz after 3853 changes. Counters: (2, 73, 10) Status = 0 Failed to change from 60000000 to 67333333 Hz after 1909 changes. Counters: (1, 30, 10) Status = 0 Failed to change from 72000000 to 85555555 Hz after 335 changes. Counters: (1, 36, 10) Status = 0 Failed to change from 72000000 to 81090909 Hz after 5629 changes. Counters: (1, 36, 10) Status = 0 Failed to change from 94000000 to 73600000 Hz after 6051 changes. Counters: (1, 47, 10) Status = 0 Failed to change from 68000000 to 96800000 Hz after 63 changes. Counters: (1, 34, 10) Status = 0 Failed to change from 100000000 to 84000000 Hz after 6660 changes. Counters: (1, 50, 10) Status = 0 Failed to change from 72666666 to 67833333 Hz after 696 changes. Counters: (3, 109, 10)  

 

Has anyone experienced this before?
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Altera_Forum
Honored Contributor I
22 Views

I think I may have fixed it. I added a read of the status register *before* setting any counter registers, and the device is now up to 15 million PLL frequency changes without a failure.

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