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Altera_Forum
Honored Contributor I
1,734 Views

PLL's in Cyclone V

Hello, 

 

I am trying to use the output of a PLL to drive a logic in FPGA. I'm not sure which clock should be connected as the 'refclk' for the PLL and how the 'outclk' of the PLL should clock my logic. 

I have tried using a 50MHz clock (PIN AF_14) as a refclk for the PLL, and used the PLL 'outclk' as a clock input but my logic does produce any output. Could you please help? 

Also, when I check my logic in ModelSim, the correct results are obtained. 

 

Thank you.
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11 Replies
Altera_Forum
Honored Contributor I
95 Views

Hi, 

 

Are you using development kit? 

Check/Monitor the clock 50Mhz refclk input Using signal-tap for the debug. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
95 Views

Hi Anand, 

 

I used the Signal Tap to monitor the refclk of PLL and looks like it is not being clocked. Seems strange as I connected the top level input clock port to the instantiated PLL (Altera-PLL).  

I think I am missing some information about dedicated clocks for PLL's. 

 

The board is Arrow SoCkit evaluation with Cyclone 5. Board Number: 5CSX5C6D631C6
Altera_Forum
Honored Contributor I
95 Views

Hi, 

 

Reference clock pin is wrong. 

Assign AC18 and check. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
95 Views

Hello Anand, 

 

Since my logic output is being sent to a HSMC pin (Bank 8A), I am using clock K14 now which is a dedicated PLL clock input (this is being used a refclk), could you help me understand how the connections are to be made to the PLL dedicated clock output (PIN A10 or A11) which can be used as the PLL 'clkout' to drive my logic. 

 

Thanks a lot for your help.
Altera_Forum
Honored Contributor I
95 Views

Hi, 

 

Do you have any daughter card connected to board?(In HSMC interface)? 

 

Because K14 pin is not having any oscillator on board,It should be from daughter cards. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
95 Views

Hi, 

 

The clocks on your board are derived from the Si5338 Oscillator . The pins that are connected to the FPGA are : Y26, AF14, AA16, K14. These are the 50MHz clocks that are connected from the Si5338 to the FPGA. You could try any of these. These are the clock assignments from the QSF file for the board.. 

 

set_location_assignment PIN_Y26 -to clk_100m_fpga 

set_location_assignment PIN_K14 -to clk_50m_fpga 

set_location_assignment PIN_AA16 -to clk_top1 

set_location_assignment PIN_AF14 -to clk_bot1 

 

set_location_assignment PIN_AA26 -to hsmc_clkin_p[1] 

 

set_location_assignment PIN_H15 -to hsmc_clkin_p[2] 

 

set_location_assignment PIN_E7 -to hsmc_clkout_p[1] 

 

set_location_assignment PIN_A11 -to hsmc_clkout_p[2] 

set_location_assignment PIN_J14 -to hsmc_clk_in0 

set_location_assignment PIN_AD29 -to hsmc_clk_out0 

 

After making the pin assignments, you need to make sure that the PLL in your design is using the clock from the mentioned pins. Also check if there are any Jumpers/ settings for clock selection on the board.
Altera_Forum
Honored Contributor I
95 Views

Hello eapenabrm, 

 

I measured the outclk of the PLL using Signal Tap, looks like it is generating some signal. Although there is no output at the HSMC pin (PIN_B13), this is where I measure the signal for all the logic I have implemented till date (it worked fine up until I started using PLL's). I have attached some screenshots to provide a better perspective of the problem. 

 

data_out is where I measure the output signal on the HSMC which has a daughter board connected to it.  

 

Thank you very much for your help.
Altera_Forum
Honored Contributor I
95 Views

Hi, 

 

Output will be not available when PLL is not locked.  

 

Check the PLL configuration. 

If the input clock remains within the minimum and maximum frequency specifications, the PLL is able to 

achieve lock. 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
95 Views

Hi, 

 

Can you post larger image of the input clocks/ PLL signals and your outputs. Also put in your code in the editor window using "code" blocks so we can take a look at it. Maybe able to help you after we get a better picture of what you are trying to do here.
Altera_Forum
Honored Contributor I
95 Views

Hello, 

 

Apologies for the delay. I conducted a lot of trial and error tests. I am not sure if this is the way to go about.  

This is the top level code: 

 

module top( 

input clk, 

input rst, 

input driver_clk, 

output pll_out, 

output locked_port, 

output data 

); 

 

driver d1( 

.clk(driver_clk), 

.rst(rst), 

.data_out(data) 

); 

 

pll pll_inst ( 

.refclk (clk), // refclk.clk 

.rst (rst), // reset.reset 

.outclk_0 (pll_out), // outclk0.clk 

.locked (locked_port) // locked.export 

); 

endmodule  

 

I am using PIN_AF14(clk) as the refclk for the PLL, I am assigning the output from the PLL (outclk) to PIN_AH12 and I am using the PIN_AJ12 as the input to the 'driver' module. The scope shows the increase in frequency. But there is lotta noise and jitter in the output signal from the HSMC PIN_B13. I have also made the outclk from the PLL as GCLK. 

 

Is this the right way to go about? Thanks for all your help.
Altera_Forum
Honored Contributor I
95 Views

Hello, 

 

Apologies for the late reply. I did a lot of trial and error tests. I was able to achieve higher clock speeds. But I wanted to confirm if this is the right way. Here is the top level code: 

 

module top( 

input clk, 

input rst, 

input driver_clk, 

output pll_out, 

output locked_port, 

output data 

); 

 

 

driver d1( 

.clk(driver_clk), 

.rst(rst), 

.data_out(data) 

); 

 

pll pll_inst ( 

.refclk (clk), // refclk.clk 

.rst (rst), // reset.reset 

.outclk_0 (pll_out), // outclk0.clk 

.locked (locked_port) // locked.export 

); 

 

endmodule  

 

The pll_out port is connected to PIN_AH12 and I am using driver_clk is connected to PIN_AJ12 which is the the clock input for the driver module. The 'data' port is connected to HSMC pin 'PIN_B13' and I have also assigned the 'pll_outclk' as a GCLK. 

 

Is this the right way to go about? Because my output signal have a lot of jitters and distortions. 

 

Thanks for all your help.
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