PLLs and differential signaling with Cyclone III

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PLLs and differential signaling with Cyclone III

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I'm in the middle of prep work for my final design project for my undergraduate degree and I was wondering if someone could answer my question about differential signaling with Altera's altlvds megafunction.

So, I'm wanting to link multiple FPGAs together in a star pattern via LVDS (4+ 144-pin Cyclone IIIs to one 240-pin Cyclone III) and I'm wondering if I strictly need to have one PLL per receiver in the 240-pin device. Wouldn't it be possible to output the transmitter's clock via LVDS and use it in a global input on the 240-pin device to clock the receiver, or am I way off base?

Thanks!

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