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HT4
Beginner
632 Views

PS and JTAG combination

Is there any way I can combine PS configuration and JTAG into one connector only. I have very limit space and not able to consider to separate connectors for each way based on Intel cyclone IV development board design.

Thanks

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5 Replies
AnandRaj_S_Intel
Employee
111 Views

Hi,

 

Refer application note AN 656

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an656.pdf

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Regards

Anand

HT4
Beginner
111 Views

Thanks Anand,

it was really helpful document.

I have one more question:

in Figure 2 in the document you sent, does not talk about pins: nCONFIG, CONF_DONE and nSTATUS connections in MAX10 configuration. I believe I should follow the figure 12 in MAX10 config document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf in page 35 for these pins. Is that correct?

Thanks

AnandRaj_S_Intel
Employee
111 Views

HT4
Beginner
111 Views

I want to double check about the pin TSRT in figure 2 AN 656. I have ignored this pin completely with my FPGA EP4CGX30.

I am not sure if Intel has any other FPGA with this pin or not but I assume it is not valid for my FPGA plus I don't need to substitute it with some other pins.

Many thanks

AnandRaj_S_Intel
Employee
111 Views

​Hi,

 

Yes, you are correct. we can ignore TRST pin for EP4CGX30 FPGA.

 

The TRST pin is an optional active-low, asynchronous reset input used for Joint Test Action Group (JTAG) boundary-scan testing (BST). While the 

TRST pin can be helpful in systems that use it, it is unnecessary for the successful operation of the BST circuitry in Intel devices. download cable does not use this pin.

 

Regards

Anand

 

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