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PS configuration

I am using Cyclone IV GX with MAX10 CPLD and Quad SPI flash for PS configuration. Here is my questions:

  1. Is there any wai I can mix JTAG programming with PS configuration for FPGA? the reason is I want to use real time debugging such as signal tap logic analyzer for debugging but without JTAG it is not possible and I don't see in configuration documents. if not then how I can do real time debugging?
  2. in document UG-01082 (PFL IP core User Guide), page 10 figure 3, I assume I can use any CPLD IO to send Data and clk to FPGA pins: Data and DClk and any pin to communicate with external Flash. is that correct?
  3. there is inconsistency between the mentioned picture above and figure 8-13 in cycolne IV datasheet chapter 8 for PS configuration. I assume the picture in PFL document is accurate and I should follow it. is that correct?



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Hi HT, I think you submit the similar forum. Here is the answers for you question. hope this will help. 1. If you refer to Configuration Scheme (Table 8-3, Table 8-4 and Table 8-5 on page 172 Cyclone IV Handbook), you can combine AS, PS and JTAG together on your board. However, when you want to select which configuration scheme you want to use, you need to select the correct MSEL setting on your board. If you look at Intel Cyclone IV Dev kit schematic diagram, you can see how we design MSEL setting on our board. - Download this link & run as Administrator - Goes to <Installation directory>\kits\cycloneIVGX_4cgx150_fpga\board_design_files\cycloneIVGX_4cgx150_fpga\schematic - Open schematic diagram c4gx_f896_host_b.pdf for more details. 2 & 3. Figure 8-13 in Handbook is more accurate. CONF_DONE and nSTATUS for Cyclone IV should be Directional (open-drain) pin. For more information and details regarding pin connection, please refer to Cyclone IV Device Family Pin Connection Guidelines (Configuration/JTAG Pins section) Link for Configuration Scheme Handbook = Link for Cyclone IV Device Family Pin Connection Guidelines (Configuration/JTAG Pins section) = Thanks.
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