HalloI am trying to use the Parallel flash loader (IP) core for configuration of my FPGA using a flash device and MAX V CPLD. I have read the application note and have a understanding how to do it. The problem i am facing is in creating and compiling the PFL ip core. The application note says "Create new MAX V design, instantiate the PFL Megafunction in MAX V design, and create pin assignment". this is the part that is not working for me . How do i create a top-level design with the PFL component only? Can any one give me an example project where i can compile the PFL ip core and see how to set a MAX V project in Quatras and so on. I do all my FPGA design in Simulink and use the Altera Quatras synthesis tool to create the project and then export it directly to Altera to create the .sof file.
Hi sstrellthanks for the suggestion. I managed to do it and compile the PFL megafunction for my MAX V design. Can you please suggest me how to write a SDC file to constrain the paths. i tried using the SDC file that i wrote for my FPGA, but that does not constrain my paths. I can see from the PFL user guide that i have to set some false paths for the asynchronous paths. Can you please suggest me how to do it. i am attaching my sdc file that i wrote for the FPGA design.