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I have a MAX V (5M2210ZF324C5N) on a custom board, connected to an ONFI-compliant NAND flash (MT29F4G16ABBDAHC) on a custom board. I want to program it through the parallel flash loader IP.
I have a known-good constraint file for pin placements and IO voltages that I'm using. I created a design that has only the IO configuration and a single instance of a PFL that's set up to program NAND flash and not to configure an FPGA. Once I program this image into the CPLD, running jtagconfig shows:
dgale$ ./jtagconfig -n
1) USB-Blaster
020A40DD 5M(1270ZF324|2210Z)/EPM2210
Node 08606E00 (110:12)# 0
Design hash 27DCE4DA82D44C4F6277
But after adding a flash device in the programmer gui, trying program, read, or erase the flash fails without an error rmessage. The status bar in the programmer reads "0% (Failed)". What could cause this? How can I get more information about the error? One thing I should mention is that the flash is 4 Gbit, where the PFL IP only officially supports up to 1 Gbit. Could this be the problem? Thanks for your help
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Bumping this thread... this is a critical-path issue for us, and Altera official support has been completely unhelpful.
I should also mention that we're having this same issue with a 1 Gbit CFI NOR flash that *is* officially supported by the PFL.- Mark as New
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I have the same NAND flash with a cyclone III FPGA, does anybody know how to overcome this problem? appreciated!

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