Parallel full case on 32-bit wide data?

Altera_Forum · ‎05-22-2012

Guys,

I just ran into a switch-case where you can "case" on non-constant values. For example:


module silly(input clk,
             input  key,
             output       is_match,
             output  data_out);
   reg           data;
   reg                  m;
   reg             d;
   always @ (posedge clk)
     begin
        case (key) // synthesis parallel_case full_case
          data:
            begin
               m <= 1'b1;
               d <= data;
            end
          data:
            begin
               m <= 1'b1;
               d <= data;
            end
          default:
            begin
               m <= 1'b0;
               d <= 4'b0000;
            end
        endcase
     end
   assign is_match = m;
   assign data_out = d;
endmodule

I know people use something like that for "one hot" state machine, but there "case" values are 1 bit wide. I am wondering if you can do that on, say, 32-bit wide data. It seems for me like an easy way to implement a search given that all data is stored in registers and every "word" is unique.

Is that something that would work in real-life? Or am I being fooled by syntax?

Altera_Forum · ‎05-22-2012

There are clearer ways to write the simple compare performed in this code.

The usage of parallel_case seems confusing, because the second case statement is actually overwriting the results of the first. So it's effectively just an inverted priority, no use for this attributes. In addition, I would follow IEEE 1364.1 (Standard for Verilog RTL synthesis) that opts against usage of th full- and parallel_case attributes in synthesized Verilog.