Parametric phase delay fpga quartus

[Tom16]

I want to generate multiple signals, and they must be phase shifted. The every phase would be calculated and have to be insert in automatically. I think about using parameters, but I don't now exactly how to do it. It is even possible?
Altera cyclone II

[Farabi]

Hello,

You can use PLL to introduce phase shift delay in your signals.

link : https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/altera-phase-locked-loop-ip-core-user-guide.html

regards,

Farabi

[Tom16]

But I need signal in khz not Mhz. Is it any other way? It also can be some kind of delay.

[AGORS5]

So divide it.
Use PLL to generate MHz signal and dived it to khz signal.
Use PLL dynamic phase shift to control kHz phase shift. Taaadaaaa.

[Tom16]

Yeah but I if you divide it by counter - any phase shift on MHz signal would be negligible kHz shift. I need it to be significant. Altpll_reconfig isn't available, if it is what you meant.

[AGORS5]

PLL has user interface for on-the-fly phase shift control. You can change it without reconfiguration with 96ps steps min.
So divide c0 and C1 separatelly. Then you can change phase shift between then on the fly.

[AGORS5]

Wait. What resolution do you need to achieve ? us, ns, ps?

[Tom16]

us is enough

[AGORS5]

So forget about PLL.
Use generated synchronus registers chain. Then you can define length as parametr.
Three will be always small time difference in output signal due to difference in routing. Definitelly below 5 ns im total.

[Tom16]

I will try it, thanks

[Ash_R_Intel]

Hi,

You could use a clock pass through a PLL generating multiple clocks with different phase shifts. Then use these clocks to sample the signal. Would that help you?

Regards