generating 40kHz signal on FPGA

[Kris4]

Hi, 

I'm beggining to programm FPGA Cyclone II EP2C5T144C8N board.

My question is how can I get a 40kHz signal output from 50MHz clock? (Pll isnt working)

Really looking forward to reply:)

[ak6dn]

Well, lets see. 50 MHz is 50,000,000 Hz.

And 40 Khz is 40,000 Hz.

50,000,000 / 40,000 is 1250.

So how about a divide by 1250 counter?

That enough to get you going?

[NazrulNaim_Intel]

Hi,

Thank you for reaching out. Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best Regards,

Nazrul Naim

[NazrulNaim_Intel]

Hi,

As have been mentioned by the user named ak6dn. The method is accepted and to make sure that you can achieve the desire signal output you need to create your own RTL code because the current PPL cannot lowered the frequency that much.

I hope that answers your question.

Regards,

Nazrul Naim

[NazrulNaim_Intel]

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards,

Nazrul Naim