I am using a MAX10 Dev Kit with Quartus. I want to use the FPGA to first receive packets, and then be able to extrapolate important data (namely IP and MAC addresses). I have downloaded the MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example found here. I have simulated the testbench and understand most signals and their relationships in the simulation (I'm viewing through Quartus Modelsim).
I have also used Quartus's System Console to launch the main.tcl file in the sc_tcl folder and have successfully verified the 3 tests found in this document and example.
Thirdly, I have a Linux machine which has successfully sent a packet through UDP to the FPGA, but nothing after that.
As I understand, the TSE example does not go deep enough to extract that information and I have to do it myself, but don't know where / how to actually do that. I'm familiar with packet structure and know I'll need to pass some sort of data into a register at the start of a packet, and will stop saving the information at the end of the packet, but don't know how to proceed with that.
Thanks so much in advance.
To answer your question, this is required to refer to the OSI model.
The TSE IP is supporting in the Physical layer and data link layer ( MAC), where the UDP is in the transport layer. This is NOT supported within the TSE IP. You need a processor and a stack to deal with UDP.
From the link below, you can obtain the simple socket server example (TCP) as the reference.