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Particular power evaluation of Intel FPGAs: IPs or Primitives?

_V_V_
Beginner
266 Views

Hi, i try to analyze a power consumption of particular blocks of Intel FPGA and SoC ICs. I evaluate BRAM, DSPs, ALMs, HSIOs, Clock-netw and so on.

Currently i am using IP-Cores for this purpose, i.e.:

  • a big 2-port-ram for BRAM
  • a fixed point multiplier for DSP
  • a big shift register for testing of registers
  • etc.

My questions are for example:

can i use primitives for this? Sometimes i do not need to worry about a data-path and need just connected clock network ( i.e. for BRAM: most power is consumed during clocking and not during value changing within the ram). However, if i generate a big RAM or a big shift-register for ALM-tests, the Timing analyzer reports timing failures (and some overhead is always generated).

 

Does someone have some tips, how can i do it in a right way?

 

My point of interest is the IC them-self and not an application on it. Currently i test 6 ICs from Intel.

 

Thanks and best regards from Germany

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2 Replies
CheePin_C_Intel
Employee
103 Views

Hi,

 

As I understand it, you seems to have some inquiries related power evaluation of Intel FPGAs on IP and Primitives. Sorry as I am not very clear of your specific inquiry, would you mind to further elaborate on it?

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

 

CheePin_C_Intel
Employee
103 Views

Hi,

 

Just would like to follow up with you on this. Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

 

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