I encountered a very puzzling problem. The FPGA code is compiled and downloaded to the Cyclone chip with JTAG, then the Cyclone hardware system is verified to be functional as expected. The same FPGA code is then converted to be an RBF file, then this raw image file is imported and downloaded from a processor using the passive serial configuration. The Cyclone chip could self boot, the logic modules within the chip is still functioning through SignalTap, but the FPGA lost the communication to the processor. While using the JTAG, there is no such issue as losing the communication.Have you encountered situations like this before? Any suggestions or solutions?
Are you absolutely sure that it's the same fpga image which is loaded?There could potentially be a problem with the inclusion of the file in the processor boot image, and you're getting an older version. Since you have jtag access you could put a constant (e.g. git sha1) into a probe and read it out using jtag in both cases. Then you know for sure it's the same image. Could the process of downloading get your software into a different software state than when you simply download the image using jtag? A good place to start would be to check the state of the communication interface using signaltap in the two cases.