Phase Relationship after PLL reconfiguration in CycloneIV

[Altera_Forum]

Hi, 

I am using EP4CE55 FPGA in my project. i have problem with PLL usage. I have enabled reconfiguration and dynamic phase shift of PLL. i want to know after i reconfigure PLL to output a different frequency, what happens to the phase relationship between output clocks. for example, the PLL C0 output 240MHz, C1 output 48MHz, and the phase differs 90 degrees, now i reconfigure the PLL C0 to output 200MHz and C1 to output 40MHz, what then the relationship between these two clocks(200MHz and 40MHz), will they still maintain the 90 degrees relationship? or will they revert back to 0 degree phase?  The CycloneIV handbook says below: "When the phase relationship between output clocks is important, Alterarecommends resynchronizing the PLL using the areset signal. This resets all internal PLL counters and re-initiates the locking process."    what does this mean? i still do not understand what on earth the phase relationship is? I use oscilloscope to check the phase relationship before and after PLL reconfiguration, i find the phase relationship is totally unregular.  pls help.  best wishes, ingdxdy

[Altera_Forum]

iirc the phase relationship once you change the pll settings can differ from what you set in the megafunction but after holding the pll in reset it should be back to your phase settings. note only hold the pll in reset not the pll reconfig.  

 if you havent already, look at  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an661.pdf

[Altera_Forum]

Thanks for your reply. 

 the doc you point to is about 28-nm devices, not CycloneIV, i think cycloneIV is very different to CycloneV device.  and you mean when resetting PLL(hold areset high for some time), the phase relationship will revert back to the setting which i initially set in megawizard? according to the signals grasped by oscilloscope, this is not the case.  i set the original phase relationship to 0 degree, however, when i reconfigure PLL to a different frequency(in this process, i hold areset high, then released), then check the phase relationship, i found there is a phase shift between two clocks, and this puzzles me much. further more, when i reconfigure to another frequency, the phase shift also changes!  another point i want to clear is that i directly register in the 144-bit chain to reconfigure the PLL to change the output frequency, the output frequency is correct everytime which i checked with oscilloscope.   is there any document discuss this issue? or did i miss something?  thanks, ingdxdy