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Altera_Forum
Honored Contributor I
803 Views

Pin Unconstrained with LOANER HPS

Hi. 

 

I've created a system with Qsys. In this system, I used the loaner options to can use the HPS's UART pins. I have my schematic file with I/O pins but i after the compilation appeers this Warning Warning (332060): Node: CLK was determined to be a clock but was found without an associated clock assignment. Info (13166): Register System:inst|System_hps_0:hps_0|System_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga_light_weight~FF_3764 is being clocked by CLK 

 

Can somebody help me please? 

 

And I have second question: if i wanna add more symbols, like a register, and state machine... where i should connect them to my generated system by Qsys? I mean, i have three ports generated: the hps_0_h2f_loan_io, hps_io and uart_0_external_connection, where can i connect the next part of the complete system? 

 

thanks
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Altera_Forum
Honored Contributor I
17 Views

The first issue is a timing constraint issue. It sounds like you're missing a clock constraint for that clock in your .sdc file. 

 

For your second question, if this extra logic is to be accessible by the Arm processor, you need to connect them to a processor bridge (regular or lightweight) or use the additional GPIOs to the processor available from the FPGA manager of the HPS. If this extra logic does not need to be accessed by the HPS and you're asking about just connecting it to I/O pins, that would be handled in the Pin Planner. Setting up HPS dedicated pins as loaner I/O makes them available to FPGA logic.