I found a relatively easier way to assign pins on FPGA for DDR2 interface, here are the steps:
- Create a quartus project and open SOPC builder.
- Add NIOS II processor (select RISC 32-bit with no bells and whistles) and modify CLK_0 as per your design.
- Add DDR2 controller from Memories and Memory Controllers->SDRAM->DDR2 SDRAM High performance controller.
- Modify parameters of DDR2 if needed (update values from datasheet).
- Double click the CPU (cpu_0 ) that you added in step 2 and update reset & exception vector by selecting the DDR2 memory controller (altmemddr_0).
- Save and generate.
- On successful generation run pin assignment tickle script in quartus (Tools->Tcl Scripts).
- The pin planner shall now show all the DDR2 pins. Assign appropriate bank to those pins (DO NOT ASSIGN PINS).
- Add instance of DDR2 controller to your top (you can copy the entity from “xxx_inst.vhd” file).
- Define all the other signals as well as add DDR2 pins created in step 8 in the port list.
- Compile project and on successful compilation open pin planner and click “show fitter placement”.
- You should see green bubbles on the bank specified in step 8.
- Back annotate all those green bubbles to complete the pin assignment. Perform visual check by looking the DQ & DQS pins. Compile the project again.
