Hello everybody,i'm using an FPGA 10M25SCE144I7G and i found this problem: the output xxx in pin location 27 is too close to PLL clock input pin in pin location 26. Is it possible to disregard this problem? Right now the pin 27 is a clock enable pin used for a crystal that gives the clock for the PLL, so this pin it is always fixed at a certain logic level and it is not dangerous for the PLL. Thank you for your attention
Hello,I have similar issue.. Error (18496): The Output o_ctrl in pin location 92 (pad_5895) is too close to PLL clock input pin (i_reset_l) in pin location 91 (pad_0) In Assignment editor, I've set I/O Maximum Toggle Rate to 0 mhz for both o_ctrl and i_reset_l, but am still getting error. Is there a way to tell Quartus not to analyze signal integrity for these two signals?
This error could be due to the EMI considerations/interference of Clock pins. In general, we do not route any other signal pin or even another clock pin close to a high frequency clock as it may cause the signal in question to shift/toggle in an unwanted manner causing glitches to appear in the output. In ASIC we normally add in a layer of isolation between clock pins/routes and other signal routes to prevent this interference.In FPGAs we can avoid this situation by separating the pin assignments for clock inputs/outputs from the PLL and other signals. I guess, it's not always possible to do so after the board has been designed, but in general these considerations will be done during Board design in order to place a "safe" distance between the free running HF clocks and other sensitive signals. If you get this error from the tool, check if you can ignore this and proceed with the bit file generation, if not, you will have to change the signal pin placement and move it away from the PLL clock inputs/outputs. -Abr