Please help me about the Cyclone 3. EP3C10TQ144

[Altera_Forum]

EP3C10TQ144 

 I've never used FPGA.  I have a problem with the use of Cyclone 3.  How to use JTAG.  How DIY JTAG cable that goes from the computer.   Now I have to create your own board.  I do not understand that Q nstatus, CONF_DONE is low at all times.  Program FPGA I have not done it.  But the problem is the AP most of my design wrong I'll try to a JTAG.  And if possible would like to see examples of design  I promise to try to turn to the FPGA.

[Altera_Forum]

I don't understand what you are looking for. How can you know that CONF_DONE is low at all times if you haven't created your board yet?

[Altera_Forum]

Sorry I'm not good at English Language. 

board Completed. R 4.7k to VCC through CONF_DONE pin.

[Altera_Forum]

nStatus, CONF_DONE (and IO_INIT_DONE) should all be tied to VCC with a resistor (10k here). 

What tells you CONF_DONE is low?

[Altera_Forum]

--- Quote Start ---  nStatus, CONF_DONE (and IO_INIT_DONE) should all be tied to VCC with a resistor (10k here). What tells you CONF_DONE is low?  --- Quote End ---   I use a Multimeter measure (^_^)

[Altera_Forum]

Are you using JTAG to configure it? What does the programmer say?

[Altera_Forum]

I think the layout circuit fault. 

Please suggest ways to design  In design time I do not have jtag.

[Altera_Forum]

You should always have a JTAG connection, it can really help. 

How do you configure the FPGA? Check the signals with a scope. You should also read Altera's recommendations and compare them with your schematic.

[Altera_Forum]

I is not done it since the beginning. 

I was assigned to. But when he came up to me to fix the problem. I looked at the manual. I saw that what they have done deficiency Now I have the problem somewhat. But what I want now is that I want to cut the rest. Out to only FPGA. Try the program before.

[Altera_Forum]

Can't you modify the board and solder a JTAG connector with the required pull ups/downs directly on the FPGA pins? It isn't very nice, but if it is just to test your design...

[Altera_Forum]

umm nStatus, CONF_DONE is low all time  

 IO_INIT_DONE must be R10k to VCC yes or no ?

[Altera_Forum]

yes it should be pulled up, and the "enable INIT_DONE output" option must be selected in the Quartus project. 

nStatus and CONF_DONE should be pulled up too, and if they stay at 0 it means that the FPGA isn't able to configure itself. Read this document (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf) for all the recommendations with the configuration signals.