Porting of Ethernet Example Desgin from Arria 10 SX to Arria 10 GX Eval Board

[LukiLeu]

I am currently trying to port the following Ethernet Example Design from the Arria 10 SX Eval Board to the Arria 10 GX Eval Board: https://www.intel.com/content/www/us/en/design-example/837384/arria-10-fpga-simple-socket-server-for-the-nios-v-m-processor-design-example.html

The Board change and IP Upgrade went fine, but when assigning the pins for the GX Board, I am running into multiple issues. 

1. The clk_enet_fpga_p should be a 125 MHz clock. I tried assinging it to the CLK_125_P (Pin BD24) which is a 125 MHz clock (according to the Userguide of the GX Board, P. 75)
   1. This results in the following error
      

      >>> Why exactly can't I use this clock? I wasn't able to figure it out?

   2. I then switched to using a different clock. The clock REFCLK_FMCA_P (Pin AN8) works. However, the clock is too fast, so I tried adding an iopll and fpll (both tried individually).
      This resulted in the same error as above.
      >>> Why can't there be any PLL in the path?
      >>> Which clock should be used in the Arria 10 GX Eval Board for the Ethernet Example?
2. Later down the implementation, the design fails again, as apparently the I/O standard for the ENET_RX_N and ENET_RX_P signals is wrong.
   The userguide (P. 80) specifies them as LVDS:
   

   1. When set to LVDS, the following error happens:
       

      >>> Why is LVDS not allowed, eventhough it is stated as LVDS in the Userguide?

   2. When changed to the proposed "High-Speed Differential I/O" the following error occurs:

      

      >>> What is the correct standard?

   3.  

I am using Quartus Prime Pro 24.3.0. 

[LukiLeu]

Does an Ethernet Example design exist for the Arria 10 GX Eval Board?

[paveetirrasrie_Intel]

Hi LukiLeu,

You may generate one from design example for A10 GX device. Please refer to link below on how to generate the design:

https://cdrdv2-public.intel.com/666633/ug-20016-683063-666633.pdf

Chapter2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices

Regards,

Pavee

[paveetirrasrie_Intel]

Hi,

Hope you're doing well.

Kindly let me know if the previous reply helps.

Regards,

pavee

[LukiLeu]

Hi, 

The example design mentioned above uses the same triple-speed IP that I used in the first attempt. With the new design, the same errors arise as in the first post.

[paveetirrasrie_Intel]

Hi LukiLeu,

Apologies for the delayed response,

I'm trying to replicate the issue but with the current board I'm working with, I'm unable to see the error.

Kindly allow me 2-3 days, I will try to port the design as per your method and will update you on this.

Regards,

Pavee

[LukiLeu]

Hi Pavee

Is there an update on this? We would really like to use the Ethernet connection on that board. At the moment, we switched to the SystemConsole, but this is awfully slow for a large amount of data.

[LukiLeu]

Hi Pavee

As we are still looking for a solution in this matter, it would be very helpful to receive an example design.

We are using this eval Board: https://www.intel.de/content/www/de/de/products/details/fpga/development-kits/arria/10-gx.html

At the moment, we are running Quartus 24.3.

The opened service request (from January, Nr. 06480193) should contain a design we tried and is not working.

[paveetirrasrie_Intel]

Hi LukiLeu,

I would suggest you to refer Golden Systems Top (Production Edition) ›, where this will provide the device pinout for use as a starting point to designing with the Arria® 10 GX FPGA Development Kit. And we do have also Installer Package (Production Edition) ›, you may check our reference design here and then match with the current design that you're trying to port over. Highly doubt that you're setting wrong pinouts, so please to our Golden System Top for pinout details.

Regards,

Pavee

[paveetirrasrie_Intel]

Hi LukiLeu,

Hope you're having good day.

Does my previous suggestion helps?

Regards,

Pavee

[LukiLeu]

Hi Pavee

Unfortunately, the provided design does not help. I am unable to fit it with Quartus 24.3.

[paveetirrasrie_Intel]

Hello,

Apologies for the delayed response.

If you check the schematic, For ethernet connection pin, you may use Bank-3C. The schematic is attached in the devkit installer package. The clk is also located in Bank-3C. I'm referring to ARRIA 10GX SI Development Board. Are we align with this?

Regards,

Pavee

[LukiLeu]

Hi Pavee,

It seems we are not really moving forward with this issue...

As mentioned above we are using the following board: https://www.intel.de/content/www/de/de/products/details/fpga/development-kits/arria/10-gx.html

According to the schematic the pins are on Bank 3A:

[paveetirrasrie_Intel]

Hello Lukileu,

Good day to you.

Apologies that the suggestions aren't resolving your issue.

I'm in mid of porting design myself at my end. Kindly allow me 1-2 days, I'll get back to you.

Regards,

Pavee

[paveetirrasrie_Intel]

Hello Lukileu,

Good day to you.

I have created new forum case 06595988. Further support will be provided in this new Forum.

Apologies for any inconvenience caused. I'll go ahead and close this forum thread.

Regards,

Pavee

[LukiLeu]

Hi Pavee

As I haven't received an answer in the case 06595988, I will post my follow up questions also here in this thread.

I just had a look at your provided qsf File. Are these pins really correct? When I look at the schematic, pin AU10 (for example) is routed to the FMCA connector instead of the Ethernet PHY.

The used schematic: https://www.intel.de/content/www/de/de/content-details/649803/arria-10-fpga-development-kit-dk-dev-10ax115s-a-board-schematic.html

Is it possible to obtain a full project instead of only the qsf File?