Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21265 Discussions

Porting of Ethernet Example Desgin from Arria 10 SX to Arria 10 GX Eval Board

LukiLeu
Beginner
224 Views

I am currently trying to port the following Ethernet Example Design from the Arria 10 SX Eval Board to the Arria 10 GX Eval Board: https://www.intel.com/content/www/us/en/design-example/837384/arria-10-fpga-simple-socket-server-for-the-nios-v-m-processor-design-example.html

 

The Board change and IP Upgrade went fine, but when assigning the pins for the GX Board, I am running into multiple issues. 

 

  1. The clk_enet_fpga_p should be a 125 MHz clock. I tried assinging it to the CLK_125_P (Pin BD24) which is a 125 MHz clock (according to the Userguide of the GX Board, P. 75)
    1. This results in the following error
      LukiLeu_0-1737463936229.png

      >>> Why exactly can't I use this clock? I wasn't able to figure it out?

    2. I then switched to using a different clock. The clock REFCLK_FMCA_P (Pin AN8) works. However, the clock is too fast, so I tried adding an iopll and fpll (both tried individually).
      This resulted in the same error as above.
      >>> Why can't there be any PLL in the path?
      >>> Which clock should be used in the Arria 10 GX Eval Board for the Ethernet Example?
  2. Later down the implementation, the design fails again, as apparently the I/O standard for the ENET_RX_N and ENET_RX_P signals is wrong.
    The userguide (P. 80) specifies them as LVDS:
    LukiLeu_2-1737464279639.png
    1. When set to LVDS, the following error happens:
       LukiLeu_3-1737464347132.png

      >>> Why is LVDS not allowed, eventhough it is stated as LVDS in the Userguide?

    2.  

      When changed to the proposed "High-Speed Differential I/O" the following error occurs:

      LukiLeu_4-1737464435879.png

      >>> What is the correct standard?

    3.  

I am using Quartus Prime Pro 24.3.0. 

 

0 Kudos
2 Replies
LukiLeu
Beginner
135 Views

Does an Ethernet Example design exist for the Arria 10 GX Eval Board?

0 Kudos
paveetirrasrie_Intel
71 Views

Hi LukiLeu,


You may generate one from design example for A10 GX device. Please refer to link below on how to generate the design:

https://cdrdv2-public.intel.com/666633/ug-20016-683063-666633.pdf

Chapter2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices


Regards,

Pavee




0 Kudos
Reply