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Post Route Timing Simulations - Why did Intel stop support?

New Contributor II


I would like to get some clarity on why Intel stopped support for post route timing simulations aka gate level timing simulations.

so far, the reasons I have been told is the following:

1.  As the devices became more complex, packed/larger, the entire chip level simulations take days or weeks to run and complete. Very time consuming and consumes lot of computing resource. 

2.  A combination of good functional simulation + timing analysis in all corners is good enough. 

3.  Most of the customers do not use it as they do not find any added value. 

4.  For high reliability designs, maybe some customers will do a "post fit netlist simulation (without any timing information).


The above reasons could be true and valid. But,

Q1) Why not still support post route simulations and provide gate-level simulation models and allow it to customer's choice to decide if he/she can do the simulations?

Q2) Yes, it will be time consuming to run these simulations, the designer can decide if he wants to spend time on it. What if I don't want to run full chip level timing simulations?  the designer can choose to pick specific critical blocks, blocks which gives problem in the hardware and choose to run a specific block level simulation according to the needs. 

Q3) A good timing constraint/timing analysis and CDC analysis is enough. But what is a good timing constraint?  I am not comfortable with understanding the in and out of a constraint file for bigger blocks, I don't know if they are good enough, so would very much like to run the post route timing simulations for specific blocks and check. 

Q4) In ASIC design, post route timing simulations are done ritually. We have the liberty to redesign and reprogram our designs, but still,For high reliability design,  I would like to include functional simulation + Timing analysis + CDC analysis + post route simulations in my toolbox. Why don't I get that option?  

Q5) Xilinx/AMD, Lattice, Microchip/Microsemi supports post route simulations. Why did Intel stop the support?




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Hi Manoj,

Thank you for you feedback and I totally get your point.

A lot of factors affecting the depreciation of post route timing simulation/gate but all I can say is more to business value and user data.

I believe this is not a short decision and probably took years to decide.

But any feedback receive which has the business' value can be considered and implemented.

I will let developer know on this and again I am apologize for the inconvenience cause.

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