Power Dissipation In FPGA

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Power Dissipation In FPGA

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I have recently implemented a crypto core in Cyclone II EP2C5T144C6 and are synthesized

using Quartus II 7.2sp3.

Using the analyzer tool, my static power dissipation is much greater than dynamic power dissipation. what does this means? and how would this differ in ASIC implementation?

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