Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

Power pin connection for Cyclone III

Altera_Forum
Honored Contributor II
1,341 Views

Hi: 

 

I am using Cyclone III EP3C25E144I7N and only banks 1, 5, and 6. I was wondering for the VCCIO pins, do I need to connect all VCCIOs to the 3.3V power supply or I just need to connect VCCIO1, VCCIO5 and VCCIO6. Also, the Cyclone® III Device Family Pin Connection Guidelines say that all VCCINTs should be connected to 1.2V. I was wondering if I could only connect those VCCIOs of the banks that I used.
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
563 Views

The device handbook tells, that all supply pins in which configuration or JTAG pins resides, are monitored by POR circuit. Also: 

 

 

--- Quote Start ---  

VCCIO for all I/O banks should be powered-up during device operation. All VCCA pins must be powered to 2.5-V (even when PLLs are not used), and must be powered-up and powered-down at the same time. VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead. 

--- Quote End ---  

0 Kudos
Altera_Forum
Honored Contributor II
563 Views

I believe that JTAG or configuration pins are in only 1 or 2 banks. So if I power the VCCIO and VCCINT pins for those banks, would it be able to pass the POR state? I don't want to connect all the VCCIOs if necessary because I have limited space in my layout.

0 Kudos
Reply