Problem using DDR3 bottom port with StratixIV EP4SGX230KF40C2

[Altera_Forum]

Hi, 

 I'm trying to introduce with SOPC_BUILDER the DDR3 64 bits in my design, that also includes NIOS 2 and flash. Analysis and synthesis go well, but when I try to run the hello_world test on NIOS there is no output. With the debugger I obtained:  mi_cmd_stack_list_frames: No stack. No symbol "new" in current context. Warning: Cannot insert breakpoint 1. Error accessing memory address 0x20000320: Unknown error 4294967295. Cannot access memory at address 0x46800000 0x20000320 is an address in memory, while 0x46800000 is the reset vector in ext_flash. I wonder if I missed something in DDR3 configuration or whatever else, as the designed with the DDR3 16 bit works and correctly runs programs on nios 2.  Thanks in advance.  ALA

[Altera_Forum]

It seems like you have an issue on Flash interface. 

You might want to double check it. Since you set the reset vector on flash, CPU will try to access flash.  Also, I'm not sure about "no output". It you are saying no stdout, then check if you have jtag-uart in your SOPC and connected correctly. Then, check in the NIOS2 SBT or IDE that your software project is properly assigned the jtag-uart for stdout or stderr.

[Altera_Forum]

--- Quote Start ---  It seems like you have an issue on Flash interface. You might want to double check it. Since you set the reset vector on flash, CPU will try to access flash.  Also, I'm not sure about "no output". It you are saying no stdout, then check if you have jtag-uart in your SOPC and connected correctly. Then, check in the NIOS2 SBT or IDE that your software project is properly assigned the jtag-uart for stdout or stderr.  --- Quote End ---    Hi, thank you for the reply. I do have jtag-uart in SOPC and stdout is correctly assigned. I attach the screenshots of my project so you can see if something is not well connected, but consider that I started from a reference design with DDR3 top port (16 bits) and modified the parameters for the DDR3 SDRAM High Performance Controller to use bottom port (64 bits). Note that the program is correctly downloded and verified: Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: OK Reading System ID at address 0x480020D8: verified Initializing CPU cache (if present) OK Downloading 20000120 ( 0%) Downloading 20010000 (98%) Downloaded 65KB in 0.5s (130.0KB/s) Verifying 20000120 ( 0%) Verifying 20010000 (98%) Verified OK Leaving target processor paused but it seems it can be started and the memory is not accessible with the debugger.

[Altera_Forum]

Which Quartus version are you using? 

I see you have 2 uart(s) in a SOPC. As far as I recall, there was an issue that the SBT will mess up with multiple connection points in Q10.0. It seems like OK in 10.1.   If you remove one of the uart, it may work.   https://www.alteraforum.com/forum/attachment.php?attachmentid=3641

[Altera_Forum]

Hi nekojiru, 

thanks for the suggestion, I removed the unused uart, unfortunately nothing has changed, hello_world doesn't work yet. I also tried to use both the top (16bits) and bottom(64bits) and on this system we ran a memory_test example on NIOS from the ddr3_top (I mean all the elf sections and stack and heap on the ddr3_top) trying accessing memory locations on the ddr3_bot. In this case the program starts but stalls when accessing any ddr3_bot location. I'm still suspecting some mis-configuration of the memory controller or something related to the clock phase, but everything seems ok. Any idea?      --- Quote Start ---  Which Quartus version are you using? I see you have 2 uart(s) in a SOPC. As far as I recall, there was an issue that the SBT will mess up with multiple connection points in Q10.0. It seems like OK in 10.1.   If you remove one of the uart, it may work.   https://www.alteraforum.com/forum/attachment.php?attachmentid=3641   --- Quote End ---  

[Altera_Forum]

I also tried to move to Quartus 10.1 with no results, no hello_world! :cry: 

 Does anyone know where I can find a reference design instantiating both NIOS and DDR3 64bits in SOPC?   Thanks ALA

[Altera_Forum]

You might want to distinguish the issue from DDR. 

I feel like that is just a SBT issue.  Try building simple design, which only contains, CPU, OnChipMem, and jtag-uart. If you can not see any hello world, then it is tool or software issue. The other way is to use LED if the program is really working even though no-output. You can write very simple design that on/off LED from software, so you won't see any command line response, but at least you can confirm that the software is running properly in FPGA.

[Altera_Forum]

Hi there! 

I added the onchip mem and ran the program from there (all the elf section on the onchip, as well as stack, heap, exeption vector) keeping the ddr3 bottom untouched: I CAN see the hello world print, that is everything works if I do not use the ddr3 bottom. If the program (or some routine, as in the case the exception vector is located on ddr3) tries to access that memory the program stalls. If it's not a problem of memory configuration in SOPC, I can also think about a wrong interaction between ddr3 and NIOS SBT, but where? Let me remind that I have no problem with the ddr3 top...  Please, help!  ALA

[Altera_Forum]

So now it is clear that the issue is on DDR3 bot. 

Have you tried the BTS GUI and run the DDR3 test on it? If it does not work for the bot, then it will be the board issue. If it runs, then your design has something wrong.  You should be able to copy the DDR3 setting from the bts example design. If you are using Q10.0 or newer, then you need to add few new setting in order to make it work correctly. I think Q9.x does not have tFaw and few more.

[Altera_Forum]

Hi Nekojiru, 

I compared the DDR3 configuration values with those on the BTS design and I actually found a few differences: after some tuning now the memory is readable and the hello_world works! Thank you for your help!  ALA