Problem with AXI Timeout Bridge

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Problem with AXI Timeout Bridge

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I have a Qsys system with HPS connected to Avalon slaves with a AXI Timeout bridge in between (hps - AXI Timeout Bridge - Avalon slaves) to access unresponsive slaves. (Cyclone V FPGA)

But the AXI timeout briege does not seems to function as expected.

Using Signal tap and System console, it was found transactions (write/read signals) are visible on the slave side of the AXI timeout bridge but not on the master side connected to slaves. The state SLAVE DEAD is high all the time. Unable to find where it has gone wrong. Is there something to do with the compatibility between the AXI4 Master and avalon MM slaves?

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