Problem with Cyclone III Remote Update IP?

Altera_Forum · ‎11-26-2008

Hi all

1) Anyone who have successfully used the Cyclone III Remote Update IP?

2) Is this ok? : Cpu run at 50MHz and IP run at 40MHz. The IP is connected directly without using a bridge

problem:

When I write "1" to register 20, my Cyclone III becomes reconfigured with the factory image. Always. Even if write the flash device offset of my user image stored in flash into register 4.

I have tried both 2 and 3 bits of right-shift as well as different offset addresses. The watchdog is disabled.

I might have a kind of interface problem since reading the core does not seem to work. When I for instance write to register 2(Watchdog timeout) or 4(Boot address), the read value does not change??

I do get some warnings during CPU generation:

1) .....object "read_source" assigned a value never read (repeats for all signals of the IP)

2) object busy used but never assigned

3) data_out[xx] at ... has no driver or initial value. using a default initial value '0'

Note: When I connect the Remote Update IP to the CPU through a clock-crossing bridge, I can still force a FPGA reconfig by writing "1" to register 4, but I do only read "-1" from all regs of the IP.

Regards

Jan

Norway

Altera_Forum · ‎11-27-2008

I have successfully used the Cyclone III update.

Some thoughts:

Can you try running it at 40 MHz just to be certain the 50 Mhz main clock is not the problem?

The basic steps that are working for me:

1. Set image address shifted by 2 bits to register 0x04.

2. Disable watchdog by writing 0 to register 0x03.

3. Write 1 to register 0x20.

For serial config mode, shifting the address by 2 is required. I seem to recall some Altera sample code shifting by 3, but I think this may have been for parallel configuration.