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I am trying to configure a EPCS1 through JTAG indirect. I receive the following message, which is as cryptic as the help.
[h=3]Serial Flash Loader Active Serial Memory Interface on device 1 is not granted .[/h] (id: 209075) CAUSE: You attempted to perform any operation when the Active Serial Memory Interface access granted signal in the SFL IP is set to active low. ACTION: Set the SFL ASMI access granted signal to active high. I am using a cyclone I with an EPCS1. I can configure the FPGA, but can't program the device. I have double check the wiring. Thanks for any help.Link Copied
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The message might be cryptic if you have no ASMI instance in your design. The basic altserial_flash_loader has e.g. no access granted signal. But you didn't tell about the SFL ip used in your design.
You'll be always able to program the serial flash by loading the default Altera SFL image for your device instaed of your design.- Mark as New
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--- Quote Start --- The message might be cryptic if you have no ASMI instance in your design. The basic altserial_flash_loader has e.g. no access granted signal. But you didn't tell about the SFL ip used in your design. You'll be always able to program the serial flash by loading the default Altera SFL image for your device instaed of your design. --- Quote End --- I created the JIC file using Quartus, and was trying to load the file using the Altera image through the programmer, not my file. Because of the problems, I was considering adding the ASMI to my design and see if it worked.
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Just for those who may end up with the same error. The configuration all have weak pullup resistors, and I had 10K to ground for the nCE. Changed it to ten ohms and my problem disappeared. Wish they had better comments for there error messages.
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--- Quote Start --- Just for those who may end up with the same error. The configuration all have weak pullup resistors, and I had 10K to ground for the nCE. Changed it to ten ohms and my problem disappeared. Wish they had better comments for there error messages. --- Quote End --- I doubt that the explanation is right. 10k pull-down is the Altera recommended value, and I have used it in many designs without problems. I also don't think that the dedicated nCE pin has a pull-up. If Altera didn't change the Cyclone chip (rather unlikely), there's probably a short to another I/O pin (with weak pull-up) in your design or a damaged nCE input.
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--- Quote Start --- I doubt that the explanation is right. 10k pull-down is the Altera recommended value, and I have used it in many designs without problems. I also don't think that the dedicated nCE pin has a pull-up. If Altera didn't change the Cyclone chip (rather unlikely), there's probably a short to another I/O pin (with weak pull-up) in your design or a damaged nCE input. --- Quote End --- I would have to agree it sounds funny. I have also used the 10K pulldown on many designs, but most of these designs had the connector for directly programming the EPCSx chip, not using the JTAG indirect. In addition, I have two boards that would not program, which were soldered by an exceptional technician. But when I changed the pulldown, I was able to program the chips.

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