Problem with a ddr sdram

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Problem with a ddr sdram

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Hello,

I had a design which was working. I decided to add a ddr-sdram (and a clock crossing bridge). Then I ran the same program as before in NIOSII and I have the following general error :

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

Maybe I did something wrong in the System libraries properties ?Or is there something specific to the ddr sdram that I forgot ?

Thanks in advance,

Myriam

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