Problem with port mapping in Quartus

[Altera_Forum]

Hello, 

I am trying to model a two dimensional array of registers using port mapping in quartus. I have first designed a five stage shift register for which I am getting the desired result i.e., the output appears with the fifth clock pulse after the CE is asserted. I then port mapped this shift register 16 times to get a 16x5 array. I am supposed to get the output after the fifth clock pulse but it appears after the 21st clock pulse after asserting CE. I have failed to comprehend the reason behind this anomalous behavior of my design. I would request you to please help me out. The codes for both the entities are given below.  ______________________________________________________________ Five stage shift register  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  entity MEMBLOCK is  Port ( Input : in STD_LOGIC;  CLK : in STD_LOGIC;  CLR : in STD_LOGIC;  CE : in std_logic;  Output : out STD_LOGIC); end MEMBLOCK;  architecture Behavioral of MEMBLOCK is  signal temp:std_logic_vector(4 downto 0); begin    process(CLK,CLR,Input,Temp,CE)  begin  if(clr='1') then  output <= '0';  temp<="00000";  elsif (clk'event and clk = '1' and CE= '1') then  temp(0) <= input;  temp(4 downto 1) <= temp(3 downto 0);  end if;   output <= temp(4);  end process;   end Behavioral;  ________________________________________________________________ 16x5 array  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;   entity Memoryblock is  Port ( Input : in STD_LOGIC_VECTOR (15 downto 0);  Output : out STD_LOGIC_VECTOR (15 downto 0);  CLK : in STD_LOGIC;  CLR : in STD_LOGIC;  CE : in STD_LOGIC); end Memoryblock;  architecture Behavioral of Memoryblock is  component MEMBLOCK is  Port ( Input : in STD_LOGIC;  CLK : in STD_LOGIC;  CLR : in STD_LOGIC;  CE : in std_logic;  Output : out STD_LOGIC); end component;  begin   A0 : MEMBLOCK  port map( Input(0), CLK, CLR, CE, Output(0));  A1 : MEMBLOCK  port map( Input(1), CLK, CLR, CE, Output(1));  A2 : MEMBLOCK  port map( Input(2), CLK, CLR, CE, Output(2));  A3 : MEMBLOCK  port map( Input(3), CLK, CLR, CE, Output(3));  A4 : MEMBLOCK  port map( Input(4), CLK, CLR, CE, Output(4));  A5 : MEMBLOCK  port map( Input(5), CLK, CLR, CE, Output(5));  A6 : MEMBLOCK  port map( Input(6), CLK, CLR, CE, Output(6));  A7 : MEMBLOCK  port map( Input(7), CLK, CLR, CE, Output(7));  A8 : MEMBLOCK  port map( Input(8), CLK, CLR, CE, Output(8));  A9 : MEMBLOCK  port map( Input(9), CLK, CLR, CE, Output(9));  A10 : MEMBLOCK  port map( Input(10), CLK, CLR, CE, Output(10));  A11 : MEMBLOCK  port map( Input(11), CLK, CLR, CE, Output(11));  A12 : MEMBLOCK  port map( Input(12), CLK, CLR, CE, Output(12));  A13 : MEMBLOCK  port map( Input(13), CLK, CLR, CE, Output(13));  A14 : MEMBLOCK  port map( Input(14), CLK, CLR, CE, Output(14));  A15 : MEMBLOCK  port map( Input(15), CLK, CLR, CE, Output(15));    end Behavioral; ________________________________________________________________ I would like to draw your attention to the fact that both the codes operate properly and give desired results with XILINX.

[Altera_Forum]

The only possible issue with the code, is the fact you have the CE on the same line as a the clock. Usually it is common to separate a clock enable from the clock, ie: 

  if rising_edge(clk) then if CE = '1' then ..... end if; end if;   But I doubt this is causing the issue. There is otherwise nothing wrong with the code. Im guessing the problem is elsewhere. Wherre are you seeing the problem? RTL simulation? gate level simulation? on the chip?

[Altera_Forum]

Just had another thought - you should not put the following line inside the clocked process: 

 output <= temp(4);  It should be on a line of its own outside the process.

[Altera_Forum]

Thank you Tricky for addressing my query... I have faced the problem when I was trying do Gate level Simulation. I tried with the nested if for CE as you suggested but it is still not working. I am not sure but I think this has got to do something with the software because the code has worked properly with other softwares. I have attached the image of the output with this message.

[Altera_Forum]

I have figured out the problem. In this design both the CLK and the CE have 16 fan outs. If I change atleast one such that its fan-out becomes 8 or less then the problem is sorted. However, since I am going to use this block as a part of a larger design I cannot have more than one clock. I, therefor, planned to split the fan-out of CE. I designed a CE block which produces two high outputs if the input which is the original clock enable is high. Now I used the Input and the output of these blocks as CEs. The code is given here 

 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;   entity Memoryblock is  Port ( Input : in STD_LOGIC_VECTOR (15 downto 0);  Output : out STD_LOGIC_VECTOR (15 downto 0);  CLK : in STD_LOGIC;  -- CE1 : inout std_logic;  -- CE2 : inout std_logic;  CLR : in STD_LOGIC;  CE : in STD_LOGIC); end Memoryblock;  architecture Behavioral of Memoryblock is signal CE1 : std_logic; signal CE2 : std_logic;  component MEMBLOCK is  Port ( Input : in STD_LOGIC;  CLK : in STD_LOGIC;  CLR : in STD_LOGIC;  CE : in std_logic;  Output : out STD_LOGIC); end component;  component ClockEnable is  port(CE : in std_logic;  CE1 : out std_logic;  CE2 : out std_logic); end Component;  begin     C : ClockEnable  port map(CE, CE1, CE2);   A0 : MEMBLOCK  port map( Input(0), CLK, CLR, CE, Output(0));  A1 : MEMBLOCK  port map( Input(1), CLK, CLR, CE, Output(1));  A2 : MEMBLOCK  port map( Input(2), CLK, CLR, CE, Output(2));  A3 : MEMBLOCK  port map( Input(3), CLK, CLR, CE, Output(3));  A4 : MEMBLOCK  port map( Input(4), CLK, CLR, CE, Output(4));  A5 : MEMBLOCK  port map( Input(5), CLK, CLR, CE1, Output(5));  A6 : MEMBLOCK  port map( Input(6), CLK, CLR, CE1, Output(6));  A7 : MEMBLOCK  port map( Input(7), CLK, CLR, CE1, Output(7));   A8 : MEMBLOCK  port map( Input(8), CLK, CLR, CE1, Output(8));  A9 : MEMBLOCK  port map( Input(9), CLK, CLR, CE1, Output(9));  A10 : MEMBLOCK  port map( Input(10), CLK, CLR, CE1, Output(10));  A11 : MEMBLOCK  port map( Input(11), CLK, CLR, CE2, Output(11));   A12 : MEMBLOCK  port map( Input(12), CLK, CLR, CE2, Output(12));  A13 : MEMBLOCK  port map( Input(13), CLK, CLR, CE2, Output(13));  A14 : MEMBLOCK  port map( Input(14), CLK, CLR, CE2, Output(14));  A15 : MEMBLOCK  port map( Input(15), CLK, CLR, CE2, Output(15));   end Behavioral;  The problem is if I use the CE1 and CE2 as signals then the CE has again a fan-out of 16. I have to use them as inout ports which is a little difficult as the block is part of a larger design. How can I sort my problem out? Please help!!!

[Altera_Forum]

I'm curious why in your process do you depend on Input and Temp? 

 Ex: process(CLK, CLR, Input, Temp, CE) ...  Wouldn't you only need the process to depend on clk, clr and ce variation?  ~doddy

[Altera_Forum]

so another weird issue... (not even sure if you check these forums anymore but whatever)... You are using a structural way to define components but call the architecture type 'Behavioral' (architecture behavioral of memoryblock is).. This might be throwing you off. 

 Your original shift register is indeed behavioral as it uses a process that sequentially executes. If you are trying to use that behavioral inside a structural, maybe that's a problem.. I wouldn't know since I'm a noob to VHDL but just looking at your naming convention does seem to be confusing and perhaps there is something you are overlooking between the two different ways to generate your logic.  ~doddy