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Altera_Forum
Honored Contributor I
1,061 Views

Problem with simulation and implementation of code in DE0 Nano Cyclone IV kit

Hi everyone, I have a kit DE0 Nano Cyclone IV EP4CE22F17C6, it has among other things 8 leds and I am programming in Quartus 12 and for simulate I am using ModelSim Starter 10.0d. My program generates a signal of 8 bits with different patterns. I have done succesfully the Syntensis of my program in Quartus and I created a testbech that generates a signal of 1MHz (that is the only "in signal" that uses my entity) and the simulation works great at the ModelSim. The problem is when I try to test the program in the kit, I use the 8 leds to see the pattern of the 8 bit signal generated and it does not work at all. For testing the code in the kit I created a pll in Quartus that generates a signal of 1MHz, and I ckecked and the pll does generate the signal of 1MHz. What is happening???? In the pictures I post the compilation in quartus and the simulation in ModelSim.

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10 Replies
Altera_Forum
Honored Contributor I
56 Views

The pictures you have posted are far too small to see anything. 

But can you also elaborate on what the problem is. Can you post some code? Can you explain what you expect to see what what actually happens?
Altera_Forum
Honored Contributor I
56 Views

Could you post your code also. Not having any other input other than a clock signal sounds sketchy. Also post the Synthesis logs.

Altera_Forum
Honored Contributor I
56 Views

Hi Abenitez, 

 

1. Check the pin assignments for led's and clock.  

2. Use signal-tap and check the behavior of the outputs. 

if you are getting the required waveform. 

Then decreases the frequency so that the changes are visible at led's. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

 

Altera_Forum
Honored Contributor I
56 Views

Hi everyone: 

The kit was ok, and the pin assingments are fine because I tested with other program and it works perfectly. But it seems that I did not have de .sdc. (the analysis and sinthesis gave me critical warnings about this) I searched online I found how to do it, and now I am doing it (by the way I do not understand very much what is the objective of it).  

I did not post de code here because it has a size of 300 lines and it will be very complicated to follow it. I did my program one step at a time and tested at ModelSim with a testbench, but the problem was I suposed that would be enough and when I checked on the board it was to late and the code was too big. I will perform the analysis and synthesis of smaller parts of my program with the .sdc file created and I will post here the results. I will do what Anand says, wait for news guys. Thanks in advance and sorry for my english. http://www.alteraforum.com/forum//images/icons/icon10.png
Altera_Forum
Honored Contributor I
56 Views

Well here I am again... I follow your advises and I reduced my code in order to see where the error was, and and if I did not found any error I continued the development, but now I am in a crash. Let me explain what I am trying to do. My goal is to create a sinusoidal pattern in a matrix of 168 leds, that way one led will be on while the rest are off in an instant of time, the movement of the light will create the sinusoidal pattern, the frequency and the amplitude (number of leds used) of the pattern are variables and are suministrated in the "in signal" datos, in this stage I am not doing that, so I simule with the variable "seudodatos" this parameters. In order to create the sinusoidal pattern I created a function that calculates the arcsin of the signal, so that way I obtain the time that one led should be on, once that time is consumed I recalculated the time for the next led in the matrix (the sinusoidal pattern has variable speed). Here is my problem. 

The first code I post here works perfectly, I am even seeing the leds of my kit blinking with a sinusoidal pattern right now, but when I update the code (this is the second code that I will submit in a second post) it gives me errors.  

Here is the code: 

---- This one works perfectly----- library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; entity estimulador is port(--load: in std_logic; --done,estado_prueba: out bit; --datos: in std_logic_vector(7 downto 0); clk: in std_logic; salida: out unsigned (7 downto 0)); end estimulador; architecture estimulador_arch of estimulador is TYPE ROM IS ARRAY(0 TO 169) OF unsigned(7 DOWNTO 0); TYPE LED IS ARRAY(0 TO 7) OF integer; TYPE FRECUENCIA_REAL IS ARRAY(0 TO 13) OF real; TYPE SINUSOIDE IS ARRAY(0 TO 167) OF integer; constant num_led:LED:=(18,36,54,72,94,116,140,168); constant freq_prueba:FRECUENCIA_REAL:=(0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5); constant uno: unsigned:="00000001"; signal seudo_salida: unsigned(7 downto 0); constant freq_proc: real:=1000000.0; -------------------------------------------------------------------------- -------------------- FUNCTION FOR CREATING A ROM ------------------------- FUNCTION INIT_ROM RETURN ROM IS VARIABLE romvar: ROM; variable suma_salida: unsigned (7 downto 0):=(others => '0'); begin for i in ROM'range loop romvar(i):= suma_salida; suma_salida:= suma_salida + uno; end loop; return romvar; end; -------------------------------------------------------------------------- CONSTANT rom_salida: ROM := INIT_ROM; -------------------------------------------------------------------------- -------------- FUNCTION FOR READING FROM THE ROM CREATED ----------------- FUNCTION LEER_ROM (cont: integer) RETURN unsigned IS variable salidat: unsigned(7 downto 0); begin salidat:= rom_salida(cont); return salidat; end; -------------------------------------------------------------------------- ---------- FUNCTION FOR CREATING AN ARRAY OF VALUES ---------------------- ----------------- FOR THE SINUSOIDAL PATTERN ----------------------------- FUNCTION SIN_INIT (amplitud,frecuencia:integer) RETURN SINUSOIDE IS variable tabla_sin:SINUSOIDE; variable cantidad_led:integer:=num_led(amplitud); variable cantidad_frec:real:=freq_prueba(frecuencia); variable limite:integer:=cantidad_led/2-1; variable calculo, diferencia:integer:=0; begin for i in 0 to limite loop calculo:=integer((arcsin(real(i+1)/real(cantidad_led/2))/(2.0 * MATH_PI * cantidad_frec))*freq_proc); tabla_sin(i):=calculo-diferencia; tabla_sin(cantidad_led-1-i):=calculo-diferencia; diferencia:=calculo; end loop; if(cantidad_led<168) then for k in cantidad_led to 167 loop tabla_sin(k):=0; end loop; end if; return tabla_sin; end; ------------------------------------------------------------------------- signal sentido: boolean:=true; begin --body of the architecture PROCESS(clk) variable tipo_prueba: std_logic_vector(1 downto 0):="10"; variable mostrar, cnt, cnt_sac, recorrido, contador_sin: integer:=0; variable paso_led, cant_led, offset, centro: integer; variable primeravez: boolean:=true; variable tabla_sinusoide:SINUSOIDE; variable seudodatos1: std_logic_vector(7 downto 0):="00000100"; variable seudodatos2: std_logic_vector(7 downto 0):="00000001"; variable amplitud_bit: std_logic_vector(2 downto 0); variable frecuencia_bit: std_logic_vector(3 downto 0); variable numero_led, frecuencia_prueba:integer; begin if(rising_edge(clk)) then cnt:=cnt+1; if(primeravez=true) then amplitud_bit:=seudodatos1(4)&seudodatos1(3)&seudodatos1(2); frecuencia_bit:=seudodatos2(6)&seudodatos2(5)&seudodatos2(4)&seudodatos2(3); numero_led:=to_integer(unsigned(amplitud_bit)); frecuencia_prueba:=to_integer(unsigned(frecuencia_bit)); if(tipo_prueba="10") then tabla_sinusoide:=SIN_INIT(numero_led,frecuencia_prueba); contador_sin:=0; paso_led:=tabla_sinusoide(contador_sin); else null; -- I check some parameters in here. I "null it" for this publication because does not worth to analyze them end if; primeravez:=false; cant_led:=num_led(numero_led); recorrido:=cant_led/2; offset:=84; centro:=84; else if(cnt=paso_led) then cnt:=0; CASE tipo_prueba IS WHEN "00" => null; -- I check some parameters in here. I "null it" for this publication because does not worth to analyze them WHEN "01" => null; -- I check some parameters in here. I "null it" for this publication because does not worth to analyze them WHEN OTHERS=>if(sentido=true) then offset:=offset+1; if(offset=centro+recorrido) then sentido<=false; end if; elsif(sentido=false) then offset:=offset-1; if(offset=centro-recorrido) then sentido<=true; end if; end if; contador_sin:=contador_sin+1; if(contador_sin=cant_led) then contador_sin:=0; end if; paso_led:=tabla_sinusoide(contador_sin); end CASE; end if; seudo_salida<= LEER_ROM(offset); end if; end if; end process; salida<=seudo_salida; end estimulador_arch;
Altera_Forum
Honored Contributor I
56 Views

This is the one with errors. If you guys read the errors it seems to be pretty clear that it is an error with arcsin function and the real number calculus, but if you compare the codes they have the same calculus and the only changes are the variables in the process. I do not know what I am doing wrong in this code. Please any help would be apreciate it. 

Here are is the code: 

library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; entity estimulador is port(--load: in std_logic; --done,estado_prueba: out bit; --datos: in std_logic_vector(7 downto 0); clk: in std_logic; salida: out unsigned (7 downto 0)); end estimulador; architecture estimulador_arch of estimulador is TYPE ROM IS ARRAY(0 TO 169) OF unsigned(7 DOWNTO 0); TYPE LED IS ARRAY(0 TO 7) OF integer; TYPE FRECUENCIA_REAL IS ARRAY(0 TO 13) OF real; TYPE SINUSOIDE IS ARRAY(0 TO 167) OF integer; constant num_led:LED:=(18,36,54,72,94,116,140,168); constant freq_prueba:FRECUENCIA_REAL:=(0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5); constant uno: unsigned:="00000001"; signal seudo_salida: unsigned(7 downto 0); constant freq_proc: real:=1000000.0; -------------------------------------------------------------------------- -------------------- FUNCTION FOR CREATING A ROM ------------------------- FUNCTION INIT_ROM RETURN ROM IS VARIABLE romvar: ROM; variable suma_salida: unsigned (7 downto 0):=(others => '0'); begin for i in ROM'range loop romvar(i):= suma_salida; suma_salida:= suma_salida + uno; end loop; return romvar; end; -------------------------------------------------------------------------- CONSTANT rom_salida: ROM := INIT_ROM; -------------------------------------------------------------------------- -------------- FUNCTION FOR READING FROM THE ROM CREATED ----------------- FUNCTION LEER_ROM (cont: integer) RETURN unsigned IS variable salidat: unsigned(7 downto 0); begin salidat:= rom_salida(cont); return salidat; end; -------------------------------------------------------------------------- ---------- FUNCTION FOR CREATING AN ARRAY OF VALUES ---------------------- ----------------- FOR THE SINUSOIDAL PATTERN ----------------------------- FUNCTION SIN_INIT (amplitud,frecuencia:integer) RETURN SINUSOIDE IS variable tabla_sin:SINUSOIDE; variable cantidad_led:integer:=num_led(amplitud); variable cantidad_frec:real:=freq_prueba(frecuencia); variable limite:integer:=cantidad_led/2-1; variable calculo, diferencia:integer:=0; begin for i in 0 to limite loop calculo:=integer((arcsin(real(i+1)/real(cantidad_led/2))/(2.0 * MATH_PI * cantidad_frec))*freq_proc); tabla_sin(i):=calculo-diferencia; tabla_sin(cantidad_led-1-i):=calculo-diferencia; diferencia:=calculo; end loop; if(cantidad_led<168) then for k in cantidad_led to 167 loop tabla_sin(k):=0; end loop; end if; return tabla_sin; end; ------------------------------------------------------------------------- signal sentido: boolean:=true; signal seudodatos1: std_logic_vector(7 downto 0):="00000100"; signal seudodatos2: std_logic_vector(7 downto 0):="00000001"; signal seudodatos3: std_logic_vector(7 downto 0):="10000000"; signal comandos: std_logic_vector(7 downto 0); begin -- body of the architecture PROCESS(clk) variable amplitud_bit: std_logic_vector(2 downto 0); variable frecuencia_bit: std_logic_vector(3 downto 0); variable tipo_comando, tipo_prueba: std_logic_vector(1 downto 0); variable mostrar, cnt, cnt_sac, recorrido, contador_sin: integer:=0; variable paso_led, cant_led, offset, centro: integer; variable primeravez: boolean:=true; variable tabla_sinusoide:SINUSOIDE; variable numero_led, frecuencia_prueba:integer; variable contador_tramas: integer range 0 to 4; begin if(rising_edge(clk)) then if(contador_tramas=0) then comandos<=seudodatos1; elsif(contador_tramas=1) then comandos<=seudodatos2; else comandos<=seudodatos3; end if; tipo_comando:=comandos(7)&comandos(0); if(tipo_comando="00") then contador_tramas:=1; tipo_prueba:= seudodatos1(6)&seudodatos1(5); amplitud_bit:= seudodatos1(4)&seudodatos1(3)&seudodatos1(2); elsif(tipo_comando="01") then contador_tramas:=2; frecuencia_bit:= seudodatos2(6)&seudodatos2(5)&seudodatos2(4)&seudodatos2(3); numero_led:=to_integer(unsigned(amplitud_bit)); frecuencia_prueba:=to_integer(unsigned(frecuencia_bit)); if(tipo_prueba="10") then tabla_sinusoide:=SIN_INIT(numero_led,frecuencia_prueba); contador_sin:=0; paso_led:=tabla_sinusoide(contador_sin); else null; -- I check some parameters in here. I "null it" for this publication because does not worth to analyze them end if; cant_led:=num_led(numero_led); recorrido:=cant_led/2; offset:=84; centro:=84; elsif(tipo_comando="10") then cnt:=cnt+1; if(cnt=paso_led) then cnt:=0; CASE tipo_prueba IS WHEN "00" => null; -- I check some parameters in here. I "null it" for this publication because does not worth to analyze them WHEN "01" => null; -- I check some parameters in here. I "null it" for this publication because does not worth to analyze them WHEN OTHERS=>if(sentido=true) then offset:=offset+1; if(offset=centro+recorrido) then sentido<=false; end if; elsif(sentido=false) then offset:=offset-1; if(offset=centro-recorrido) then sentido<=true; end if; end if; contador_sin:=contador_sin+1; if(contador_sin=cant_led) then contador_sin:=0; end if; paso_led:=tabla_sinusoide(contador_sin); end CASE; end if; seudo_salida<= LEER_ROM(offset); end if; end if; end process; salida<=seudo_salida; end estimulador_arch;  

These are the errors: 

Error (10414): VHDL Unsupported Feature error at estimulador.vhd(73): cannot synthesize non-constant real objects or values.  

Error (10658): VHDL Operator error at estimulador.vhd(73): failed to evaluate call to operator ""/"" 

Error (10346): VHDL error at math_real.vhd(3302): formal port or parameter "X" must have actual or default value 

Error (10657): VHDL Subprogram error at estimulador.vhd(73): failed to elaborate call to subprogram "ARCSIN" 

Error (10658): VHDL Operator error at estimulador.vhd(73): failed to evaluate call to operator ""*"" 

Error (10657): VHDL Subprogram error at estimulador.vhd(128): failed to elaborate call to subprogram "SIN_INIT" 

Error (12152): Can't elaborate user hierarchy "estimulador:inst"
Altera_Forum
Honored Contributor I
56 Views

The SIN_INIT function uses real types inside it - and you call it during real time code, which is not allowed. You can only use this to initialise constants.

Altera_Forum
Honored Contributor I
56 Views

I do not understand Tricky. In the first code (the one that works) I also call the function SIN_INIT in real time code, don't I??? What am I missing??? And how can I solve it???? Thanks in adavance for your quick answer.

Altera_Forum
Honored Contributor I
56 Views

This code is written as if it was software, and rather hard to follow.  

The SIN_INIT function should not be called in the process at all - I dont know how it is working in the first code - I get the feeling that Quartus does not support initial values on variables, and hence sets primeravez=false, and removes all of the code inside the primeravez=true section, hence causing no issues. I bet it never actually initialises the table. 

 

I highly suggest you read up on digital logic design. When you have done this - then DRAW the circuit you think you need. Then when you have this drawn circuit, the read up on how to follow templates for the circuit elements you have. 

One hint - you almost NEVER need variables - I HIGHLY recommend you make EVERYTHING a signal.
Altera_Forum
Honored Contributor I
56 Views

Thanks a lot. I will try to do that, it will be hard but I´ll try.