Problems with VHDL custom component

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Problems with VHDL custom component

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I am getting this error message

"Error: Error (10482): VHDL error at xxx.vhd(45): object "\'0\'" is used but not declared <filename.vhd> Line: 45" while generating SOPC system.

Line 45 in the code refers to a generic port declared of std_logic type and initialized to '0'. I have included following ieee libraries

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

In _hw.tcl file I have added the generic port as parameter using

add_parameter P_NAME STD_LOGIC 0 "Parameter"

Any suggestions or clue about the error message will be of great help.

Thanks a lot.

Vinayak

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