Problems with interfacing QDRII with NiosII on Stratix III devellopment board

Altera_Forum · ‎01-19-2010

Hi,

I'm trying to interface QDRII memory (CY7C1263V18-400) with my NIOS II processor using SOPC builder on my Stratix III devellopment kit.

Each time I try to add the UniPhy QDRII controller I've got the following warnings:

Warning: QDRII.avl_w: writedata[72] width must be in {8, 16, 32, 64, 128, 256, 512, 1024} for dynamic addressing

Warning: QDRII.avl_w: byteenable[8] width must be 9 (data width/8)

Warning: QDRII.avl_r: readdata[72] width must be in {8, 16, 32, 64, 128, 256, 512, 1024} for dynamic addressing

Furthermore, when I try to generate the system I obtain the error:

# 2010.01.19 13:54:53 (*) Making arbitration and system (top) modules.

ERROR:

slave data width (72) for slave QDRII/avl_r unexpected

9

Then I tried to use the DDRII (MT9HTF12872AY-800E1) but I obtained the same type of warnings and errors.

I'm dying trying to resolve this problem, can someone help me plz ?

Altera_Forum · ‎02-12-2010

Hi,

It's just one click away "Generate power-of-2 bus widths" on "Advanced Settings"

A good reference is the "External Memory Interface Handbook"

I'm also trying to use the QDR memory of Stratix III dev Kit, with NiosII and SOPC .

I still have issues with the top level connections of these pins, do we need another top level IP to drive them ?

.MEM_QDRII_afi_clk_out(),

.afi_cal_fail_from_the_MEM_QDRII(),

.afi_cal_success_from_the_MEM_QDRII(),

.afi_reset_n_from_the_MEM_QDRII(),

.dll_delayctrl_from_the_MEM_QDRII(),

.mem_doff_n_from_the_MEM_QDRII(),

.oct_rdn_to_the_MEM_QDRII(),

.oct_rup_to_the_MEM_QDRII(),

.pll_addr_cmd_clk_from_the_MEM_QDRII(),

.pll_afi_clk_from_the_MEM_QDRII(),

.pll_locked_from_the_MEM_QDRII(),

.pll_mem_clk_from_the_MEM_QDRII(),

.pll_write_clk_from_the_MEM_QDRII(),

Thanks