Programming FPGA failing

[Altera_Forum]

I m trying to debug a custom built FPGA board developed in my institution, that contains Cyclone IV EP4CE1022C8 FPGA. When programmed using UrJTAG software, it returns a warning: TDO may be stuck at 1, when "detect" command is issued and hence the JTAG chain is not detecting. rechecked all the supply voltage points in the FPGA, and its fine. What might possibly be the reason for this error that prevents from proper configuration of the device. 

 The FPGA is getting reasonably heated up when the powered up. Please help regarding the debugging of this board. Need a start. Has the FPGA gone bad, how do i find it.? Thanks in advance  Jeebu

[Altera_Forum]

The warning says it all, don't You think? TDO signal may be shorted to VCC, check that.

[Altera_Forum]

--- Quote Start ---  The warning says it all, don't You think? TDO signal may be shorted to VCC, check that.  --- Quote End ---   Thanks for the fast reply Socrates, but i ve double checked whether any of the supply pins are getting shorted with the TDO pin, and i ve just rechecked it and its NOT . So what is the next step that i should do in the debugging. There are three supply voltages for the device, 1.2,2.5 and 3.3. Supply voltages are also not shorted, nor are they shorted to the TDO pin, as i ve just said.And one more thing, What is the obvious method to check whether the FPGA has gone faulty?  Regards Jeebu

[Altera_Forum]

Any other pins shorted or not connected? I had such problem, when one wire was not conntected to the JTAG connector properly.

[Altera_Forum]

--- Quote Start ---  Any other pins shorted or not connected? I had such problem, when one wire was not conntected to the JTAG connector properly.  --- Quote End ---    I just rechecked all the connection pins. None of the JTAG pins are short nor, are they unconnected. The board is using a FT2232 USB-JTAG converter instead of USB blaster-MAX CPLD as in normal dev boards from Altera. The converter(FT2232) seems to be working, but the FPGA doesnt seem to toggle the TDO pin, when detect command is thrown, thats why the warning "TDO stuck at 1"(correct me, if i m wrong). How can i check that the FPGA is faulty or not ? Since this is a custom made board, they havent connected any LEDs for indication that it has passed the chain test. Forgive my ignorance, since i m doing board testing for the very first time.  Regards Jeebu

[Altera_Forum]

Can You attach a normal JTAG adapter to the board?

[Altera_Forum]

You should check the other JTAG signals on the FPGA pins. Check that TMS TCK and TDI are toggling correctly. Pay special attention to the TCK signal. If there are bounces that could be interpreted as additional clock edges by the FPGA then it will cause all kind of problems.

[Altera_Forum]

--- Quote Start ---  You should check the other JTAG signals on the FPGA pins. Check that TMS TCK and TDI are toggling correctly. Pay special attention to the TCK signal. If there are bounces that could be interpreted as additional clock edges by the FPGA then it will cause all kind of problems.  --- Quote End ---     Here i m attaching the clock signal probed in a DSO when a detect command is issued in UrJTAG, Dont know as to whether this clock is correct or not.Checked with another FT2232, and the clock is exaclty same as attached below. And for the TMS and TDI pin, yes they are toggling, but the TDO is stuck @ 1 as mentioned in the earlier posts.  Regards Jeebu